From: Tony Lindgren <tony@atomide.com>
To: Roger Quadros <rogerq@ti.com>
Cc: hch@lst.de, robin.murphy@arm.com, robh+dt@kernel.org, nm@ti.com,
t-kristo@ti.com, nsekhar@ti.com, linux-omap@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
stable@kernel.org
Subject: Re: [PATCH v2] ARM: dts: dra7: Add bus_dma_limit for L3 bus
Date: Fri, 13 Mar 2020 07:41:36 -0700 [thread overview]
Message-ID: <20200313144136.GA37466@atomide.com> (raw)
In-Reply-To: <20200313094717.6671-1-rogerq@ti.com>
* Roger Quadros <rogerq@ti.com> [200313 02:48]:
> The L3 interconnect's memory map is from 0x0 to
> 0xffffffff. Out of this, System memory (SDRAM) can be
> accessed from 0x80000000 to 0xffffffff (2GB)
>
> DRA7 does support 4GB of SDRAM but upper 2GB can only be
> accessed by the MPU subsystem.
>
> Add the dma-ranges property to reflect the physical address limit
> of the L3 bus.
>
> Issues ere observed only with SATA on DRA7-EVM with 4GB RAM
> and CONFIG_ARM_LPAE enabled. This is because the controller
> supports 64-bit DMA and its driver sets the dma_mask to 64-bit
> thus resulting in DMA accesses beyond L3 limit of 2G.
>
> Setting the correct bus_dma_limit fixes the issue.
Thanks applying into fixes.
Tony
next prev parent reply other threads:[~2020-03-13 14:41 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-13 9:47 [PATCH v2] ARM: dts: dra7: Add bus_dma_limit for L3 bus Roger Quadros
2020-03-13 14:41 ` Tony Lindgren [this message]
2020-03-13 15:05 ` Robin Murphy
2020-03-13 15:15 ` Tony Lindgren
2020-03-16 8:35 ` Roger Quadros
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