From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82D39C5ACD6 for ; Wed, 18 Mar 2020 06:24:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4E6C920752 for ; Wed, 18 Mar 2020 06:24:29 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=flygoat.com header.i=jiaxun.yang@flygoat.com header.b="YAwbhbFk" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727110AbgCRGY2 (ORCPT ); Wed, 18 Mar 2020 02:24:28 -0400 Received: from sender3-op-o12.zoho.com.cn ([124.251.121.243]:17879 "EHLO sender3-op-o12.zoho.com.cn" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726553AbgCRGY2 (ORCPT ); Wed, 18 Mar 2020 02:24:28 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1584512602; s=mail; d=flygoat.com; i=jiaxun.yang@flygoat.com; h=From:To:Cc:Message-ID:Subject:Date:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Content-Type; bh=lqxLmQ9H2IRyfO54vBbJaAbVkunOdiQogdl3xWHjoWY=; b=YAwbhbFk042/uNjBfn1Yn863yLk21s23wCnztqpQz4wViY3n53p6aZ4AjTBGms7U XAqt1ySDuJQD5qH07jIIW68lqA4RPeQ0/jQm+ZmX3Qykz4rr7YN6dnnit1v52rq2Di+ S7sE+/X4BkUYAEYiWVQPN8DB+BHqae8MCATKaqOc= Received: from localhost.localdomain (39.155.141.144 [39.155.141.144]) by mx.zoho.com.cn with SMTPS id 1584512599214438.5675020621534; Wed, 18 Mar 2020 14:23:19 +0800 (CST) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: Jiaxun Yang , Huacai Chen , Rob Herring , Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , Mark Rutland , Ralf Baechle , Paul Burton , Allison Randal , Greg Kroah-Hartman , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Message-ID: <20200318062102.8145-4-jiaxun.yang@flygoat.com> Subject: [PATCH v5 03/11] dt-bindings: interrupt-controller: Add Loongson LIOINTC Date: Wed, 18 Mar 2020 14:20:31 +0800 X-Mailer: git-send-email 2.26.0.rc2 In-Reply-To: <20200318062102.8145-1-jiaxun.yang@flygoat.com> References: <20200318062102.8145-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoCNMailClient: External Content-Type: text/plain; charset=utf8 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Document Loongson I/O Interrupt controller. Co-developed-by: Huacai Chen Signed-off-by: Jiaxun Yang Reviewed-by: Rob Herring --- .../loongson,liointc.yaml | 93 +++++++++++++++++++ 1 file changed, 93 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/= loongson,liointc.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongso= n,liointc.yaml b/Documentation/devicetree/bindings/interrupt-controller/loo= ngson,liointc.yaml new file mode 100644 index 000000000000..9c6b91fee477 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,lioin= tc.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/interrupt-controller/loongson,liointc.= yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Loongson Local I/O Interrupt Controller + +maintainers: + - Jiaxun Yang + +description: | + This interrupt controller is found in the Loongson-3 family of chips as = the primary + package interrupt controller which can route local I/O interrupt to inte= rrupt lines + of cores. + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +properties: + compatible: + oneOf: + - const: loongson,liointc-1.0 + - const: loongson,liointc-1.0a + + reg: + maxItems: 1 + + interrupt-controller: true + + interrupts: + description: + Interrupt source of the CPU interrupts. + minItems: 1 + maxItems: 4 + + interrupt-names: + description: List of names for the parent interrupts. + items: + - const: int0 + - const: int1 + - const: int2 + - const: int3 + minItems: 1 + maxItems: 4 + + '#interrupt-cells': + const: 2 + + 'loongson,parent_int_map': + description: | + This property points how the children interrupts will be mapped into= CPU + interrupt lines. Each cell refers to a parent interrupt line from 0 = to 3 + and each bit in the cell refers to a children interrupt fron 0 to 31= . + If a CPU interrupt line didn't connected with liointc, then keep it'= s + cell with zero. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array + - items: + minItems: 4 + maxItems: 4 + + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - 'loongson,parent_int_map' + + +examples: + - | + iointc: interrupt-controller@3ff01400 { + compatible =3D "loongson,liointc-1.0"; + reg =3D <0x3ff01400 0x64>; + + interrupt-controller; + #interrupt-cells =3D <2>; + + interrupt-parent =3D <&cpuintc>; + interrupts =3D <2>, <3>; + interrupt-names =3D "int0", "int1"; + + loongson,parent_int_map =3D <0xf0ffffff>, /* int0 */ + <0x0f000000>, /* int1 */ + <0x00000000>, /* int2 */ + <0x00000000>; /* int3 */ + + }; + +... --=20 2.26.0.rc2