From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.6 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB3B2C4332B for ; Fri, 20 Mar 2020 03:36:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9CFEE20724 for ; Fri, 20 Mar 2020 03:36:42 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="wX3eXeSN" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726956AbgCTDgl (ORCPT ); Thu, 19 Mar 2020 23:36:41 -0400 Received: from mail27.static.mailgun.info ([104.130.122.27]:12548 "EHLO mail27.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726603AbgCTDgl (ORCPT ); Thu, 19 Mar 2020 23:36:41 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1584675400; h=Message-Id: Date: Subject: Cc: To: From: Sender; bh=znBJGhFi3/HMKJ6NsPkvkKTgdVlBcafwD2Un8aWndTg=; b=wX3eXeSNJhOjckI1aDEC1L4UdwskQps2pTteMaJeegi/tp2UAxnW3eJTO4aPtCwTyI/5LPH8 QjO7ScoayTyKkNUYIjPFkweddd0sbzGxVTDoLNwe/jnB/W9hjaF/Oqb1qK/z5ptE+FnaZ9Eq HlV8FKMd/9VWys2sR+0Et1ZZ/pI= X-Mailgun-Sending-Ip: 104.130.122.27 X-Mailgun-Sid: WyI0MWYwYSIsICJsaW51eC1rZXJuZWxAdmdlci5rZXJuZWwub3JnIiwgImJlOWU0YSJd Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by mxa.mailgun.org with ESMTP id 5e743a3c.7f7fe2817b58-smtp-out-n05; Fri, 20 Mar 2020 03:36:28 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id BE01AC44788; Fri, 20 Mar 2020 03:36:26 +0000 (UTC) Received: from jordan-laptop.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse) by smtp.codeaurora.org (Postfix) with ESMTPSA id 1DC4CC433D2; Fri, 20 Mar 2020 03:36:16 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 1DC4CC433D2 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: linux-arm-msm@vger.kernel.org Cc: John Stultz , smasetty@codeaurora.org, Brian Masney , Christoph Hellwig , Daniel Vetter , David Airlie , Douglas Anderson , "Michael J. Ruhl" , Rob Clark , Rob Herring , Sean Paul , Stephen Boyd , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 0/2] msm/gpu/a6xx: use the DMA-API for GMU memory allocations Date: Thu, 19 Mar 2020 21:36:09 -0600 Message-Id: <20200320033611.7623-1-jcrouse@codeaurora.org> X-Mailer: git-send-email 2.17.1 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When CONFIG_INIT_ON_ALLOC_DEFAULT_ON the GMU memory allocator runs afoul of cache coherency issues because it is mapped as write-combine without clearing the cache after it was zeroed. Rather than duplicate the hacky workaround we use in the GEM allocator for the same reason it turns out that we don't need to have a bespoke memory allocator for the GMU anyway. It uses a flat, global address space and there are only two relatively minor allocations anyway. In short this is essentially what the DMA API was created for so replace a bunch of memory management code with two calls to allocate and free DMA memory and we're fine. In a previous version of this series I added the dma-ranges property to the device tree file for the GMU and updated the bindings to YAML. Rob correctly pointed out that we didn't need dma-ranges any more but I'm still pushing the YAML conversion because it is good and we'll eventually need it anyway so why not. v6: Check return value of dma_set_mask_and_coherent per Christoph Hellwig v5: Refresh on Brian Masney's patch that removes sram from gmu.txt [1] v4: Use dma_alloc_wc() wrappers per Michael Ruhl. v3: Fix YAML description per RobH and remove dma-ranges and replace it with the correct DMA mask in the GMU device. Convert the iova type to a dma_attr_t to make it 32 bit friendly. v2: Fix the example bindings for dma-ranges - the third item is the size Pass false to of_dma_configure so that it fails probe if the DMA region is not set up. [1] https://patchwork.freedesktop.org/patch/356869/?series=74446&rev=1 Jordan Crouse (2): dt-bindings: display: msm: Convert GMU bindings to YAML drm/msm/a6xx: Use the DMA API for GMU memory objects .../devicetree/bindings/display/msm/gmu.txt | 65 --------- .../devicetree/bindings/display/msm/gmu.yaml | 123 ++++++++++++++++++ drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 115 ++-------------- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 6 +- 4 files changed, 137 insertions(+), 172 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/msm/gmu.txt create mode 100644 Documentation/devicetree/bindings/display/msm/gmu.yaml -- 2.17.1