From: Alexandre Ghiti <alex@ghiti.fr>
To: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>, Zong Li <zong.li@sifive.com>,
Anup Patel <anup@brainfault.org>, Christoph Hellwig <hch@lst.de>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Cc: Alexandre Ghiti <alex@ghiti.fr>
Subject: [RFC PATCH 6/7] dt-bindings: riscv: Remove "riscv,svXX" property from device-tree
Date: Sun, 22 Mar 2020 07:00:27 -0400 [thread overview]
Message-ID: <20200322110028.18279-7-alex@ghiti.fr> (raw)
In-Reply-To: <20200322110028.18279-1-alex@ghiti.fr>
This property can not be used before virtual memory is set up
and then the distinction between sv39 and sv48 is done at runtime
using SATP csr property: this property is now useless, so remove it.
Signed-off-by: Alexandre Ghiti <alex@ghiti.fr>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 13 -------------
1 file changed, 13 deletions(-)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 04819ad379c2..12baabbac213 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -39,19 +39,6 @@ properties:
Identifies that the hart uses the RISC-V instruction set
and identifies the type of the hart.
- mmu-type:
- allOf:
- - $ref: "/schemas/types.yaml#/definitions/string"
- - enum:
- - riscv,sv32
- - riscv,sv39
- - riscv,sv48
- description:
- Identifies the MMU address translation mode used on this
- hart. These values originate from the RISC-V Privileged
- Specification document, available from
- https://riscv.org/specifications/
-
riscv,isa:
allOf:
- $ref: "/schemas/types.yaml#/definitions/string"
--
2.20.1
next prev parent reply other threads:[~2020-03-22 11:06 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-22 11:00 [RFC PATCH 0/7] Introduce sv48 support Alexandre Ghiti
2020-03-22 11:00 ` [RFC PATCH 1/7] riscv: Get rid of compile time logic with MAX_EARLY_MAPPING_SIZE Alexandre Ghiti
2020-03-26 6:10 ` Anup Patel
2020-04-03 15:17 ` Palmer Dabbelt
2020-04-07 5:12 ` Alex Ghiti
2020-03-22 11:00 ` [RFC PATCH 2/7] riscv: Allow to dynamically define VA_BITS Alexandre Ghiti
2020-03-26 6:12 ` Anup Patel
2020-04-03 15:17 ` Palmer Dabbelt
2020-04-07 5:12 ` Alex Ghiti
2020-03-22 11:00 ` [RFC PATCH 3/7] riscv: Simplify MAXPHYSMEM config Alexandre Ghiti
2020-03-26 6:22 ` Anup Patel
2020-03-26 6:34 ` Anup Patel
2020-04-03 15:53 ` Palmer Dabbelt
2020-04-07 5:13 ` Alex Ghiti
2020-03-22 11:00 ` [RFC PATCH 4/7] riscv: Implement sv48 support Alexandre Ghiti
2020-03-26 7:00 ` Anup Patel
2020-03-31 16:31 ` Alex Ghiti
2020-04-03 15:53 ` Palmer Dabbelt
2020-04-07 5:14 ` Alex Ghiti
2020-04-07 5:56 ` Anup Patel
2020-04-08 4:39 ` Alex Ghiti
2020-04-08 5:06 ` Anup Patel
2020-03-22 11:00 ` [RFC PATCH 5/7] riscv: Use pgtable_l4_enabled to output mmu type in cpuinfo Alexandre Ghiti
2020-03-26 7:01 ` Anup Patel
2020-04-03 15:53 ` Palmer Dabbelt
2020-04-07 5:14 ` Alex Ghiti
2020-03-22 11:00 ` Alexandre Ghiti [this message]
2020-03-26 7:03 ` [RFC PATCH 6/7] dt-bindings: riscv: Remove "riscv,svXX" property from device-tree Anup Patel
2020-04-03 15:53 ` Palmer Dabbelt
2020-04-07 5:14 ` Alex Ghiti
2020-03-22 11:00 ` [RFC PATCH 7/7] riscv: Explicit comment about user virtual address space size Alexandre Ghiti
2020-03-26 7:05 ` Anup Patel
2020-04-03 15:53 ` Palmer Dabbelt
2020-04-07 5:15 ` Alex Ghiti
2020-03-31 19:53 ` [RFC PATCH 0/7] Introduce sv48 support Palmer Dabbelt
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