From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Sergey.Semin@baikalelectronics.ru
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Jiri Slaby <jslaby@suse.com>,
Serge Semin <fancer.lancer@gmail.com>,
Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>,
Maxim Kaurkin <Maxim.Kaurkin@baikalelectronics.ru>,
Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>,
Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>,
Ekaterina Skachko <Ekaterina.Skachko@baikalelectronics.ru>,
Vadim Vlasov <V.Vlasov@baikalelectronics.ru>,
Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
Paul Burton <paulburton@kernel.org>,
Ralf Baechle <ralf@linux-mips.org>,
Maxime Ripard <mripard@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
Ray Jui <rjui@broadcom.com>,
Scott Branden <sbranden@broadcom.com>,
Florian Fainelli <f.fainelli@gmail.com>,
Wei Xu <xuwei5@hisilicon.com>,
Jason Cooper <jason@lakedaemon.net>, Andrew Lunn <andrew@lunn.ch>,
Gregory Clement <gregory.clement@bootlin.com>,
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
Jisheng Zhang <Jisheng.Zhang@synaptics.com>,
Heiko Stuebner <heiko@sntech.de>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
Russell King <linux@armlinux.org.uk>,
linux-arm-kernel@lists.infradead.org,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
linux-clk@vger.kernel.org,
Heikki Krogerus <heikki.krogerus@linux.intel.com>,
Kefeng Wang <wangkefeng.wang@huawei.com>,
linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2] serial: 8250_dw: Fix common clocks usage race condition
Date: Mon, 23 Mar 2020 11:20:51 +0200 [thread overview]
Message-ID: <20200323092051.GB1922688@smile.fi.intel.com> (raw)
In-Reply-To: <20200323024611.16039-1-Sergey.Semin@baikalelectronics.ru>
On Mon, Mar 23, 2020 at 05:46:09AM +0300, Sergey.Semin@baikalelectronics.ru wrote:
> From: Serge Semin <Sergey.Semin@baikalelectronics.ru>
The question to CLK framework maintainers, is it correct approach in general
for this case?
> There are races possible in the dw8250_set_termios() callback method
> and while the device is in PM suspend state. A race condition may
> happen if the baudrate clock source device is shared with some other
> device (in our machine it's another DW UART port). In this case if that
> device changes the clock rate while serial console is using it the
> DW 8250 UART port might not only end up with an invalid uartclk value
> saved, but may also experience a distorted output data since baud-clock
> could have been changed. In order to fix this lets enable an exclusive
> reference clock rate access in case if "baudclk" device is specified.
>
> So if some other device also acquires the rate exclusivity during the
> time of a DW UART 8250 port being opened, then DW UART 8250 driver
> won't be able to alter the baud-clock. It shall just use the available
> clock rate. Similarly another device also won't manage to change the
> rate at that time. If nothing else have the exclusive rate access
> acquired except DW UART 8250 driver, then the driver will be able to
> alter the rate as much as it needs to in accordance with the currently
> implemented logic.
Thank you for an update, my comments below.
...
> +static int dw8250_startup(struct uart_port *p)
> +{
> + struct dw8250_data *d = to_dw8250_data(p->private_data);
> +
> + /*
> + * Some platforms may provide a reference clock shared between several
> + * devices. In this case before using the serial port first we have to
> + * make sure nothing will change the rate behind our back and second
> + * the tty/serial subsystem knows the actual reference clock rate of
> + * the port.
> + */
> + if (clk_rate_exclusive_get(d->clk)) {
> + dev_warn(p->dev, "Couldn't lock the clock rate\n");
So, if this fails, in ->shutdown you will disbalance reference count, or did I
miss something?
> + } else if (d->clk) {
> + p->uartclk = clk_get_rate(d->clk);
> + if (!p->uartclk) {
> + clk_rate_exclusive_put(d->clk);
> + dev_err(p->dev, "Clock rate not defined\n");
> + return -EINVAL;
> + }
This operations I didn't get. If we have d->clk and suddenly get 0 as a rate
(and note, that we still update uartclk member!), we try to put (why?) the
exclusiveness of rate.
> + }
> +
> + return serial8250_do_startup(p);
> +}
> +
> +static void dw8250_shutdown(struct uart_port *p)
> +{
> + struct dw8250_data *d = to_dw8250_data(p->private_data);
> +
> + serial8250_do_shutdown(p);
> +
> + clk_rate_exclusive_put(d->clk);
> +}
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2020-03-23 9:21 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20200306130231.05BBC8030795@mail.baikalelectronics.ru>
2020-03-23 2:46 ` [PATCH v2] serial: 8250_dw: Fix common clocks usage race condition Sergey.Semin
2020-03-23 9:20 ` Andy Shevchenko [this message]
2020-03-23 11:11 ` Sergey Semin
2020-03-23 11:52 ` Andy Shevchenko
2020-03-23 17:07 ` Sergey Semin
2020-03-23 10:01 ` Maxime Ripard
2020-03-23 13:50 ` Sergey Semin
2020-03-24 9:41 ` Maxime Ripard
2020-03-24 10:12 ` Andy Shevchenko
2020-03-25 17:11 ` Sergey Semin
2020-03-26 1:44 ` Stephen Boyd
2020-03-27 9:12 ` Sergey Semin
2020-05-06 23:31 ` [PATCH v3 0/4] serial: 8250_dw: Fix ref clock usage Serge Semin
2020-05-06 23:31 ` [PATCH v3 1/4] serial: 8250: Fix max baud limit in generic 8250 port Serge Semin
2020-05-15 13:48 ` Andy Shevchenko
2020-05-06 23:31 ` [PATCH v3 2/4] serial: 8250: Add 8250 port clock update method Serge Semin
2020-05-15 12:45 ` Greg Kroah-Hartman
2020-05-15 14:32 ` Serge Semin
2020-05-06 23:31 ` [PATCH v3 3/4] serial: 8250_dw: Simplify the ref clock rate setting procedure Serge Semin
2020-05-15 14:05 ` Andy Shevchenko
2020-05-15 14:50 ` Serge Semin
2020-05-15 15:05 ` Andy Shevchenko
2020-05-06 23:31 ` [PATCH v3 4/4] serial: 8250_dw: Fix common clocks usage race condition Serge Semin
2020-05-15 14:10 ` Andy Shevchenko
2020-05-15 15:19 ` Serge Semin
2020-05-07 18:29 ` [PATCH v3 0/4] serial: 8250_dw: Fix ref clock usage Andy Shevchenko
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