From: Chris Packham <chris.packham@alliedtelesis.co.nz>
To: mpe@ellerman.id.au, robh+dt@kernel.org, mark.rutland@arm.com,
paulus@samba.org, benh@kernel.crashing.org
Cc: Hamish Martin <hamish.martin@alliedtelesis.co.nz>,
devicetree@vger.kernel.org, linuxppc-dev@lists.ozlabs.org,
linux-kernel@vger.kernel.org,
Chris Packham <chris.packham@alliedtelesis.co.nz>
Subject: [PATCH] powerpc/fsl: Add cache properties for T2080/T2081
Date: Wed, 25 Mar 2020 10:36:12 +1300 [thread overview]
Message-ID: <20200324213612.31614-1-chris.packham@alliedtelesis.co.nz> (raw)
Add the d-cache/i-cache properties for the T208x SoCs. The L1 cache on
these SoCs is 32KiB and is split into 64 byte blocks (lines).
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---
arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi b/arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi
index 3f745de44284..2ad27e16ac16 100644
--- a/arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi
@@ -81,6 +81,10 @@ cpus {
cpu0: PowerPC,e6500@0 {
device_type = "cpu";
reg = <0 1>;
+ d-cache-line-size = <64>;
+ i-cache-line-size = <64>;
+ d-cache-size = <32768>;
+ i-cache-size = <32768>;
clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>;
@@ -88,6 +92,10 @@ cpu0: PowerPC,e6500@0 {
cpu1: PowerPC,e6500@2 {
device_type = "cpu";
reg = <2 3>;
+ d-cache-line-size = <64>;
+ i-cache-line-size = <64>;
+ d-cache-size = <32768>;
+ i-cache-size = <32768>;
clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>;
@@ -95,6 +103,10 @@ cpu1: PowerPC,e6500@2 {
cpu2: PowerPC,e6500@4 {
device_type = "cpu";
reg = <4 5>;
+ d-cache-line-size = <64>;
+ i-cache-line-size = <64>;
+ d-cache-size = <32768>;
+ i-cache-size = <32768>;
clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>;
@@ -102,6 +114,10 @@ cpu2: PowerPC,e6500@4 {
cpu3: PowerPC,e6500@6 {
device_type = "cpu";
reg = <6 7>;
+ d-cache-line-size = <64>;
+ i-cache-line-size = <64>;
+ d-cache-size = <32768>;
+ i-cache-size = <32768>;
clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>;
--
2.25.1
next reply other threads:[~2020-03-24 21:36 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-24 21:36 Chris Packham [this message]
2020-03-25 1:59 ` [PATCH] powerpc/fsl: Add cache properties for T2080/T2081 Michael Ellerman
2020-03-25 2:08 ` Scott Wood
2020-03-25 2:38 ` Chris Packham
2020-03-25 2:50 ` Chris Packham
2020-03-25 3:18 ` [PATCH v2] powerpc/setup_64: Set cache-line-size based on cache-block-size Chris Packham
2020-04-16 4:36 ` Chris Packham
2020-04-16 11:43 ` Michael Ellerman
2020-04-16 21:28 ` Chris Packham
2020-04-20 2:53 ` Michael Ellerman
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