[PATCH 0/4] clocksource: Fix MIPS GIC and DW APB Timer for Baikal-T1 SoC support

[PATCH 0/4] clocksource: Fix MIPS GIC and DW APB Timer for Baikal-T1 SoC support

[Sergey.Semin]

From: Serge Semin <fancer.lancer@gmail.com>

Aside from MIPS-specific r4k timer Baikal-T1 chip also provides a functionality
of two another timers: embedded into the MIPS GIC timer and three external DW
timers available over APB bus. But we can't use them before the corresponding
drivers are properly fixed. First of all DW APB Timer shouldn't be bound to a
single CPU, since as being accessible over APB they are external with respect
to all possible CPUs. Secondly there might be more than just two DW APB Timers
in the system (Baikal-T1 has three of them), so permit the driver to use one of
them as a clocksource and the rest - for clockevents. Thirdly it's possible to
use MIPS GIC timer as a clocksource so register it in the corresponding
subsystem (the patch has been found in the Paul Burton MIPS repo so I left the
original Signed-off-by attribute). Finally in the same way as r4k timer the
MIPS GIC timer should be used with care when CPUFREQ config is enabled since in
case of CM2 the timer counting depends on the CPU reference clock frequency
while the clocksource subsystem currently doesn't support the timers with
non-stable clock.

This patchset is rebased and tested on the mainline Linux kernel 5.6-rc4:
commit 98d54f81e36b ("Linux 5.6-rc4").

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Signed-off-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Maxim Kaurkin <Maxim.Kaurkin@baikalelectronics.ru>
Cc: Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>
Cc: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Cc: Ekaterina Skachko <Ekaterina.Skachko@baikalelectronics.ru>
Cc: Vadim Vlasov <V.Vlasov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-kernel@vger.kernel.org

Paul Burton (1):
  clocksource: mips-gic-timer: Register as sched_clock

Serge Semin (3):
  clocksource: dw_apb_timer: Set clockevent any-possible-CPU mask
  clocksource: dw_apb_timer_of: Fix missing clockevent timers
  clocksource: mips-gic-timer: Set limitations on
    clocksource/sched-clocks usage

 drivers/clocksource/dw_apb_timer.c    | 18 +++++++---------
 drivers/clocksource/dw_apb_timer_of.c |  9 +++-----
 drivers/clocksource/mips-gic-timer.c  | 30 ++++++++++++++++++++++-----
 include/linux/dw_apb_timer.h          |  2 +-
 4 files changed, 36 insertions(+), 23 deletions(-)

-- 
2.25.1

[PATCH v2 0/6] clocksource: Fix MIPS GIC and DW APB Timer for Baikal-T1 SoC support

[Sergey.Semin]

From: Serge Semin <fancer.lancer@gmail.com>

As for all Baikal-T1 SoC related patchsets, which need this, we replaced
the DW APB Timer legacy plain text-based dt-binding file with DT schema.
Similarly the MIPS GIC bindings file is also converted to DT schema seeing
it also defines the MIPS GIC Timer binding.

Aside from MIPS-specific r4k timer Baikal-T1 chip also provides a
functionality of two another timers: embedded into the MIPS GIC timer and
three external DW timers available over APB bus. But we can't use them
before the corresponding drivers are properly fixed. First of all DW APB
Timer shouldn't be bound to a single CPU, since as being accessible over
APB they are external with respect to all possible CPUs. Secondly there
might be more than just two DW APB Timers in the system (Baikal-T1 has
three of them), so permit the driver to use one of them as a clocksource
and the rest - for clockevents. Thirdly it's possible to use MIPS GIC
timer as a clocksource so register it in the corresponding subsystem
(the patch has been found in the Paul Burton MIPS repo so I left the
original Signed-off-by attribute). Finally in the same way as r4k timer
the MIPS GIC timer should be used with care when CPUFREQ config is enabled
since in case of CM2 the timer counting depends on the CPU reference clock
frequency while the clocksource subsystem currently doesn't support the
timers with non-stable clock.

This patchset is rebased and tested on the mainline Linux kernel 5.6-rc4:
commit 98d54f81e36b ("Linux 5.6-rc4").

Changelog v2:
- Fix the SoB tags.
- Our corporate email server doesn't change Message-Id anymore, so the
  patchset is resubmitted being in the cover-letter-threaded format.
- Convert the "snps,dw-apb-timer" binding to DT schema in a dedicated
  patch.
- Convert the "mti,gic" binding to DT schema in a dedicated patch.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Maxim Kaurkin <Maxim.Kaurkin@baikalelectronics.ru>
Cc: Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>
Cc: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Cc: Ekaterina Skachko <Ekaterina.Skachko@baikalelectronics.ru>
Cc: Vadim Vlasov <V.Vlasov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Alessandro Zummo <a.zummo@towertech.it>
Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: linux-rtc@vger.kernel.org
Cc: linux-kernel@vger.kernel.org

Paul Burton (1):
  clocksource: mips-gic-timer: Register as sched_clock

Serge Semin (5):
  dt-bindings: rtc: Convert snps,dw-apb-timer to DT schema
  dt-bindings: interrupt-controller: Convert mti,gic to DT schema
  clocksource: dw_apb_timer: Set clockevent any-possible-CPU mask
  clocksource: dw_apb_timer_of: Fix missing clockevent timers
  clocksource: mips-gic-timer: Set limitations on
    clocksource/sched-clocks usage

 .../interrupt-controller/mips-gic.txt         |  67 --------
 .../interrupt-controller/mti,gic.yaml         | 152 ++++++++++++++++++
 .../devicetree/bindings/rtc/dw-apb.txt        |  32 ----
 .../bindings/rtc/snps,dw-apb-timer.yaml       |  88 ++++++++++
 drivers/clocksource/dw_apb_timer.c            |  18 +--
 drivers/clocksource/dw_apb_timer_of.c         |   9 +-
 drivers/clocksource/mips-gic-timer.c          |  30 +++-
 include/linux/dw_apb_timer.h                  |   2 +-
 8 files changed, 276 insertions(+), 122 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml
 delete mode 100644 Documentation/devicetree/bindings/rtc/dw-apb.txt
 create mode 100644 Documentation/devicetree/bindings/rtc/snps,dw-apb-timer.yaml

-- 
2.25.1

[PATCH v2 1/6] dt-bindings: rtc: Convert snps,dw-apb-timer to DT schema

[Sergey.Semin]

From: Serge Semin <Sergey.Semin@baikalelectronics.ru>

Modern device tree bindings are supposed to be created as YAML-files
in accordance with DT schema. This commit replaces Synopsys DW Timer
legacy bare text binding with YAML file. As before the binding file
states that the corresponding dts node is supposed to be compatible
with generic DW APB Timer indicated by the "snps,dw-apb-timer"
compatible string and to provide a mandatory registers memory range,
one timer interrupt, either reference clock source or a fixed clock
rate value. It may also have an optional APB bus reference clock
phandle specified.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Alessandro Zummo <a.zummo@towertech.it>
Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: linux-rtc@vger.kernel.org

---

I have doubts that this binding file belongs to the bindings/rtc
directory seeing it's a pure timer with no rtc facilities like
days/months/years counting and alarms. What about moving it to the
"Documentation/devicetree/bindings/timer/" directory?

I also don't know who is the corresponding driver maintainer, so I added
Daniel Lezcano to the maintainers schema. Any idea what email should be
specified there instead?

Please also note, that "oneOf: - required: ..." pattern isn't working
here. So if you omit any of the clock-related property the
dt_binding_check procedure won't fail. Seeing the anyOf schema is working
I suppose this happens due to the dtschema/lib.py script, which replaces
the global oneOf with a fixup for the interrupts/interrupts-extended
properties:

> def fixup_interrupts(schema):
>    # Supporting 'interrupts' implies 'interrupts-extended' is also supported.
>    if not 'interrupts' in schema['properties'].keys():
>        return
>
>    # Any node with 'interrupts' can have 'interrupt-parent'
>    schema['properties']['interrupt-parent'] = True
>
>    schema['properties']['interrupts-extended'] = { "$ref": "#/properties/interrupts" };
>
>    if not ('required' in schema.keys() and 'interrupts' in schema['required']):
>        return
>
!>    # Currently no better way to express either 'interrupts' or 'interrupts-extended'
!>    # is required. If this fails validation, the error reporting is the whole
!>    # schema file fails validation
!>    schema['oneOf'] = [ {'required': ['interrupts']}, {'required': ['interrupts-extended']} ]
---
 .../devicetree/bindings/rtc/dw-apb.txt        | 32 -------
 .../bindings/rtc/snps,dw-apb-timer.yaml       | 88 +++++++++++++++++++
 2 files changed, 88 insertions(+), 32 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/rtc/dw-apb.txt
 create mode 100644 Documentation/devicetree/bindings/rtc/snps,dw-apb-timer.yaml

diff --git a/Documentation/devicetree/bindings/rtc/dw-apb.txt b/Documentation/devicetree/bindings/rtc/dw-apb.txt
deleted file mode 100644
index c703d51abb6c..000000000000
--- a/Documentation/devicetree/bindings/rtc/dw-apb.txt
+++ /dev/null
@@ -1,32 +0,0 @@
-* Designware APB timer
-
-Required properties:
-- compatible: One of:
- 	"snps,dw-apb-timer"
-	"snps,dw-apb-timer-sp" <DEPRECATED>
-	"snps,dw-apb-timer-osc" <DEPRECATED>
-- reg: physical base address of the controller and length of memory mapped
-  region.
-- interrupts: IRQ line for the timer.
-- either clocks+clock-names or clock-frequency properties
-
-Optional properties:
-- clocks	: list of clock specifiers, corresponding to entries in
-		  the clock-names property;
-- clock-names	: should contain "timer" and "pclk" entries, matching entries
-		  in the clocks property.
-- clock-frequency: The frequency in HZ of the timer.
-- clock-freq: For backwards compatibility with picoxcell
-
-If using the clock specifiers, the pclk clock is optional, as not all
-systems may use one.
-
-
-Example:
-	timer@ffe00000 {
-		compatible = "snps,dw-apb-timer";
-		interrupts = <0 170 4>;
-		reg = <0xffe00000 0x1000>;
-		clocks = <&timer_clk>, <&timer_pclk>;
-		clock-names = "timer", "pclk";
-	};
diff --git a/Documentation/devicetree/bindings/rtc/snps,dw-apb-timer.yaml b/Documentation/devicetree/bindings/rtc/snps,dw-apb-timer.yaml
new file mode 100644
index 000000000000..88d939ed1b0b
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/snps,dw-apb-timer.yaml
@@ -0,0 +1,88 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rtc/snps,dw-apb-timer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synopsys DesignWare APB Timer
+
+maintainers:
+  - Daniel Lezcano <daniel.lezcano@linaro.org>
+
+properties:
+  compatible:
+    oneOf:
+      - const: snps,dw-apb-timer
+      - enum:
+          - snps,dw-apb-timer-sp
+          - snps,dw-apb-timer-osc
+        deprecated: true
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    minItems: 1
+    items:
+       - description: Timer ticks reference clock source
+       - description: APB interface clock source
+
+  clock-names:
+    minItems: 1
+    items:
+      - const: timer
+      - const: pclk
+
+  clock-frequency: true
+
+  clock-freq:
+    $ref: "/schemas/types.yaml#/definitions/uint32"
+    description: |
+      Has the same meaning as the 'clock-frequency' property - timer clock
+      frequency in HZ, but is defined only for the backwards compatibility
+      with the picoxcell platform.
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+oneOf:
+  - required:
+      - clocks
+      - clock-names
+  - required:
+      - clock-frequency
+  - required:
+      - clock-freq
+
+examples:
+  - |
+    timer@ffe00000 {
+      compatible = "snps,dw-apb-timer";
+      interrupts = <0 170 4>;
+      reg = <0xffe00000 0x1000>;
+      clocks = <&timer_clk>, <&timer_pclk>;
+      clock-names = "timer", "pclk";
+    };
+  - |
+    timer@ffe00000 {
+      compatible = "snps,dw-apb-timer";
+      interrupts = <0 170 4>;
+      reg = <0xffe00000 0x1000>;
+      clocks = <&timer_clk>;
+      clock-names = "timer";
+    };
+  - |
+    timer@ffe00000 {
+      compatible = "snps,dw-apb-timer";
+      interrupts = <0 170 4>;
+      reg = <0xffe00000 0x1000>;
+      clock-frequency = <25000000>;
+    };
+...
-- 
2.25.1

Re: [PATCH v2 1/6] dt-bindings: rtc: Convert snps,dw-apb-timer to DT schema

[Alexandre Belloni]

Hi,

On 24/03/2020 20:43:20+0300, Sergey.Semin@baikalelectronics.ru wrote:
> From: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> 
> Modern device tree bindings are supposed to be created as YAML-files
> in accordance with DT schema. This commit replaces Synopsys DW Timer
> legacy bare text binding with YAML file. As before the binding file
> states that the corresponding dts node is supposed to be compatible
> with generic DW APB Timer indicated by the "snps,dw-apb-timer"
> compatible string and to provide a mandatory registers memory range,
> one timer interrupt, either reference clock source or a fixed clock
> rate value. It may also have an optional APB bus reference clock
> phandle specified.
> 
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: Paul Burton <paulburton@kernel.org>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: Alessandro Zummo <a.zummo@towertech.it>
> Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
> Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: devicetree@vger.kernel.org
> Cc: linux-rtc@vger.kernel.org
> 
> ---
> 
> I have doubts that this binding file belongs to the bindings/rtc
> directory seeing it's a pure timer with no rtc facilities like
> days/months/years counting and alarms. What about moving it to the
> "Documentation/devicetree/bindings/timer/" directory?
> 

Exactly my reaction when seeing the patch, please move it out of
bindings/rtc/


-- 
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

Re: [PATCH v2 1/6] dt-bindings: rtc: Convert snps,dw-apb-timer to DT schema

[Serge Semin]

Hello Alexandre

On Tue, Mar 24, 2020 at 07:07:09PM +0100, Alexandre Belloni wrote:
> Hi,
> 
> On 24/03/2020 20:43:20+0300, Sergey.Semin@baikalelectronics.ru wrote:
> > From: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> > 
> > Modern device tree bindings are supposed to be created as YAML-files
> > in accordance with DT schema. This commit replaces Synopsys DW Timer
> > legacy bare text binding with YAML file. As before the binding file
> > states that the corresponding dts node is supposed to be compatible
> > with generic DW APB Timer indicated by the "snps,dw-apb-timer"
> > compatible string and to provide a mandatory registers memory range,
> > one timer interrupt, either reference clock source or a fixed clock
> > rate value. It may also have an optional APB bus reference clock
> > phandle specified.
> > 
> > Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> > Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> > Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> > Cc: Paul Burton <paulburton@kernel.org>
> > Cc: Ralf Baechle <ralf@linux-mips.org>
> > Cc: Alessandro Zummo <a.zummo@towertech.it>
> > Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
> > Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
> > Cc: Thomas Gleixner <tglx@linutronix.de>
> > Cc: Arnd Bergmann <arnd@arndb.de>
> > Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
> > Cc: Rob Herring <robh+dt@kernel.org>
> > Cc: Mark Rutland <mark.rutland@arm.com>
> > Cc: devicetree@vger.kernel.org
> > Cc: linux-rtc@vger.kernel.org
> > 
> > ---
> > 
> > I have doubts that this binding file belongs to the bindings/rtc
> > directory seeing it's a pure timer with no rtc facilities like
> > days/months/years counting and alarms. What about moving it to the
> > "Documentation/devicetree/bindings/timer/" directory?
> > 
> 
> Exactly my reaction when seeing the patch, please move it out of
> bindings/rtc/
> 

Agreed. I am pretty sure Rob find something to be fixed and the main part
of the patchset still hasn't been reviewed. So v3 will be necessary for sure.
I'll move this binding out of rtc in a dedicated patch then.

-Sergey

P.S. For some reason your email still hasn't been delivered to my corporate
email, so responding from the private one.

> 
> -- 
> Alexandre Belloni, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com

Re: [PATCH v2 1/6] dt-bindings: rtc: Convert snps,dw-apb-timer to DT schema

[Rob Herring]

On Tue, Mar 24, 2020 at 08:43:20PM +0300, Sergey.Semin@baikalelectronics.ru wrote:
> From: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> 
> Modern device tree bindings are supposed to be created as YAML-files
> in accordance with DT schema. This commit replaces Synopsys DW Timer
> legacy bare text binding with YAML file. As before the binding file
> states that the corresponding dts node is supposed to be compatible
> with generic DW APB Timer indicated by the "snps,dw-apb-timer"
> compatible string and to provide a mandatory registers memory range,
> one timer interrupt, either reference clock source or a fixed clock
> rate value. It may also have an optional APB bus reference clock
> phandle specified.
> 
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: Paul Burton <paulburton@kernel.org>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: Alessandro Zummo <a.zummo@towertech.it>
> Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
> Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: devicetree@vger.kernel.org
> Cc: linux-rtc@vger.kernel.org
> 
> ---
> 
> I have doubts that this binding file belongs to the bindings/rtc
> directory seeing it's a pure timer with no rtc facilities like
> days/months/years counting and alarms. What about moving it to the
> "Documentation/devicetree/bindings/timer/" directory?

+1

> I also don't know who is the corresponding driver maintainer, so I added
> Daniel Lezcano to the maintainers schema. Any idea what email should be
> specified there instead?
> 
> Please also note, that "oneOf: - required: ..." pattern isn't working
> here. So if you omit any of the clock-related property the
> dt_binding_check procedure won't fail. Seeing the anyOf schema is working
> I suppose this happens due to the dtschema/lib.py script, which replaces
> the global oneOf with a fixup for the interrupts/interrupts-extended
> properties:
> 
> > def fixup_interrupts(schema):
> >    # Supporting 'interrupts' implies 'interrupts-extended' is also supported.
> >    if not 'interrupts' in schema['properties'].keys():
> >        return
> >
> >    # Any node with 'interrupts' can have 'interrupt-parent'
> >    schema['properties']['interrupt-parent'] = True
> >
> >    schema['properties']['interrupts-extended'] = { "$ref": "#/properties/interrupts" };
> >
> >    if not ('required' in schema.keys() and 'interrupts' in schema['required']):
> >        return
> >
> !>    # Currently no better way to express either 'interrupts' or 'interrupts-extended'
> !>    # is required. If this fails validation, the error reporting is the whole
> !>    # schema file fails validation
> !>    schema['oneOf'] = [ {'required': ['interrupts']}, {'required': ['interrupts-extended']} ]

I'll fix this. I'll have to check for 'oneOf' and if it exists then put 
it under an 'allOf'.

> ---
>  .../devicetree/bindings/rtc/dw-apb.txt        | 32 -------
>  .../bindings/rtc/snps,dw-apb-timer.yaml       | 88 +++++++++++++++++++
>  2 files changed, 88 insertions(+), 32 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/rtc/dw-apb.txt
>  create mode 100644 Documentation/devicetree/bindings/rtc/snps,dw-apb-timer.yaml

Otherwise, looks good.

Reviewed-by: Rob Herring <robh@kernel.org>

[PATCH v2 2/6] dt-bindings: interrupt-controller: Convert mti,gic to DT schema

[Sergey.Semin]

From: Serge Semin <Sergey.Semin@baikalelectronics.ru>

Modern device tree bindings are supposed to be created as YAML-files
in accordance with DT schema. This commit replaces MIPS GIC legacy bare
text binding with YAML file. As before the binding file states that the
corresponding dts node is supposed to be compatible with MIPS Global
Interrupt Controller indicated by the "mti,gic" compatible string and
to provide a mandatory interrupt-controller and '#interrupt-cells'
properties. There might be optional registers memory range,
"mti,reserved-cpu-vectors" and "mti,reserved-ipi-vectors" properties
specified.

MIPS GIC also includes a free-running global timer, per-CPU count/compare
timers, and a watchdog. Since currently the GIC Timer is only supported the
DT schema expects an IRQ and clock-phandler charged timer sub-node with
"mti,mips-gic-timer" compatible string.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Alessandro Zummo <a.zummo@towertech.it>
Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: linux-rtc@vger.kernel.org

---

I don't really know who is the corresponding driver maintainer, so I
added to the maintainers schema Paul since he used to be looking for the
MIPS arch and Thomas looking after it now. Any idea what email should be
specified there instead?

Similarly to the previous patch the "oneOf: - required: ..." pattern isn't
working here. Supposedly due to the script' dtschema/lib.py
interrupts/interrupts-extended fixup.
---
 .../interrupt-controller/mips-gic.txt         |  67 --------
 .../interrupt-controller/mti,gic.yaml         | 152 ++++++++++++++++++
 2 files changed, 152 insertions(+), 67 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml

diff --git a/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt b/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
deleted file mode 100644
index 173595305e26..000000000000
--- a/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
+++ /dev/null
@@ -1,67 +0,0 @@
-MIPS Global Interrupt Controller (GIC)
-
-The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
-It also supports local (per-processor) interrupts and software-generated
-interrupts which can be used as IPIs.  The GIC also includes a free-running
-global timer, per-CPU count/compare timers, and a watchdog.
-
-Required properties:
-- compatible : Should be "mti,gic".
-- interrupt-controller : Identifies the node as an interrupt controller
-- #interrupt-cells : Specifies the number of cells needed to encode an
-  interrupt specifier.  Should be 3.
-  - The first cell is the type of interrupt, local or shared.
-    See <include/dt-bindings/interrupt-controller/mips-gic.h>.
-  - The second cell is the GIC interrupt number.
-  - The third cell encodes the interrupt flags.
-    See <include/dt-bindings/interrupt-controller/irq.h> for a list of valid
-    flags.
-
-Optional properties:
-- reg : Base address and length of the GIC registers.  If not present,
-  the base address reported by the hardware GCR_GIC_BASE will be used.
-- mti,reserved-cpu-vectors : Specifies the list of CPU interrupt vectors
-  to which the GIC may not route interrupts.  Valid values are 2 - 7.
-  This property is ignored if the CPU is started in EIC mode.
-- mti,reserved-ipi-vectors : Specifies the range of GIC interrupts that are
-  reserved for IPIs.
-  It accepts 2 values, the 1st is the starting interrupt and the 2nd is the size
-  of the reserved range.
-  If not specified, the driver will allocate the last 2 * number of VPEs in the
-  system.
-
-Required properties for timer sub-node:
-- compatible : Should be "mti,gic-timer".
-- interrupts : Interrupt for the GIC local timer.
-
-Optional properties for timer sub-node:
-- clocks : GIC timer operating clock.
-- clock-frequency : Clock frequency at which the GIC timers operate.
-
-Note that one of clocks or clock-frequency must be specified.
-
-Example:
-
-	gic: interrupt-controller@1bdc0000 {
-		compatible = "mti,gic";
-		reg = <0x1bdc0000 0x20000>;
-
-		interrupt-controller;
-		#interrupt-cells = <3>;
-
-		mti,reserved-cpu-vectors = <7>;
-		mti,reserved-ipi-vectors = <40 8>;
-
-		timer {
-			compatible = "mti,gic-timer";
-			interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
-			clock-frequency = <50000000>;
-		};
-	};
-
-	uart@18101400 {
-		...
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
-		...
-	};
diff --git a/Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml b/Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml
new file mode 100644
index 000000000000..1e47c0cdc231
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml
@@ -0,0 +1,152 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MIPS Global Interrupt Controller
+
+maintainers:
+  - Paul Burton <paulburton@kernel.org>
+  - Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+
+description: |
+  The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
+  It also supports local (per-processor) interrupts and software-generated
+  interrupts which can be used as IPIs. The GIC also includes a free-running
+  global timer, per-CPU count/compare timers, and a watchdog.
+
+allOf:
+  - $ref: /schemas/interrupt-controller.yaml#
+
+properties:
+  compatible:
+    const: mti,gic
+
+  "#interrupt-cells":
+    const: 3
+    description: |
+      The 1st cell is the type of interrupt: local or shared defined in the
+      file 'dt-bindings/interrupt-controller/mips-gic.h'. The 2nd cell is the
+      GIC interrupt number. The 3d cell encodes the interrupt flags setting up
+      the IRQ trigger modes, which are defined in the file
+      'dt-bindings/interrupt-controller/irq.h'.
+
+  reg:
+    description: |
+      Base address and length of the GIC registers space. If not present,
+      the base address reported by the hardware GCR_GIC_BASE will be used.
+    maxItems: 1
+
+  interrupt-controller: true
+
+  mti,reserved-cpu-vectors:
+    description: |
+      Specifies the list of CPU interrupt vectors to which the GIC may not
+      route interrupts. This property is ignored if the CPU is started in EIC
+      mode.
+    allOf:
+      - $ref: /schemas/types.yaml#definitions/uint32-array
+      - minItems: 1
+        maxItems: 6
+        uniqueItems: true
+        items:
+          minimum: 2
+          maximum: 7
+
+  mti,reserved-ipi-vectors:
+    description: |
+      Specifies the range of GIC interrupts that are reserved for IPIs.
+      It accepts two values: the 1st is the starting interrupt and the 2nd is
+      the size of the reserved range. If not specified, the driver will
+      allocate the last (2 * number of VPEs in the system).
+    allOf:
+      - $ref: /schemas/types.yaml#definitions/uint32-array
+      - items:
+          - minimum: 0
+            maximum: 254
+          - minimum: 2
+            maximum: 254
+
+patternProperties:
+  "^timer(@[0-9a-f]+)?$":
+    type: object
+    description: |
+      MIPS GIC includes a free-running global timer, per-CPU count/compare
+      timers, and a watchdog. Currently only the GIC Timer is supported.
+    properties:
+      compatible:
+        const: mti,gic-timer
+
+      interrupts:
+        description: |
+          Interrupt for the GIC local timer, so normally it's suppose to be of
+          <GIC_LOCAL X IRQ_TYPE_NONE> format.
+        maxItems: 1
+
+      clocks:
+        maxItems: 1
+
+      clock-frequency: true
+
+    required:
+      - compatible
+      - interrupts
+
+    oneOf:
+      - required:
+          - clocks
+      - required:
+          - clock-frequency
+
+    additionalProperties: false
+
+unevaluatedProperties: false
+
+required:
+  - compatible
+  - "#interrupt-cells"
+  - interrupt-controller
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/mips-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    interrupt-controller@1bdc0000 {
+      compatible = "mti,gic";
+      reg = <0x1bdc0000 0x20000>;
+      interrupt-controller;
+      #interrupt-cells = <3>;
+      mti,reserved-cpu-vectors = <7>;
+      mti,reserved-ipi-vectors = <40 8>;
+
+      timer {
+        compatible = "mti,gic-timer";
+        interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
+        clock-frequency = <50000000>;
+      };
+    };
+  - |
+    #include <dt-bindings/interrupt-controller/mips-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    interrupt-controller@1bdc0000 {
+      compatible = "mti,gic";
+      reg = <0x1bdc0000 0x20000>;
+      interrupt-controller;
+      #interrupt-cells = <3>;
+
+      timer {
+        compatible = "mti,gic-timer";
+        interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
+        clocks = <&cpu_pll>;
+      };
+    };
+  - |
+    interrupt-controller {
+      compatible = "mti,gic";
+      interrupt-controller;
+      #interrupt-cells = <3>;
+    };
+...
-- 
2.25.1

Re: [PATCH v2 2/6] dt-bindings: interrupt-controller: Convert mti,gic to DT schema

[Rob Herring]

On Tue, Mar 24, 2020 at 08:43:21PM +0300, Sergey.Semin@baikalelectronics.ru wrote:
> From: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> 
> Modern device tree bindings are supposed to be created as YAML-files
> in accordance with DT schema. This commit replaces MIPS GIC legacy bare
> text binding with YAML file. As before the binding file states that the
> corresponding dts node is supposed to be compatible with MIPS Global
> Interrupt Controller indicated by the "mti,gic" compatible string and
> to provide a mandatory interrupt-controller and '#interrupt-cells'
> properties. There might be optional registers memory range,
> "mti,reserved-cpu-vectors" and "mti,reserved-ipi-vectors" properties
> specified.
> 
> MIPS GIC also includes a free-running global timer, per-CPU count/compare
> timers, and a watchdog. Since currently the GIC Timer is only supported the
> DT schema expects an IRQ and clock-phandler charged timer sub-node with
> "mti,mips-gic-timer" compatible string.
> 
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: Paul Burton <paulburton@kernel.org>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: Alessandro Zummo <a.zummo@towertech.it>
> Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
> Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: devicetree@vger.kernel.org
> Cc: linux-rtc@vger.kernel.org
> 
> ---
> 
> I don't really know who is the corresponding driver maintainer, so I
> added to the maintainers schema Paul since he used to be looking for the
> MIPS arch and Thomas looking after it now. Any idea what email should be
> specified there instead?
> 
> Similarly to the previous patch the "oneOf: - required: ..." pattern isn't
> working here. Supposedly due to the script' dtschema/lib.py
> interrupts/interrupts-extended fixup.
> ---
>  .../interrupt-controller/mips-gic.txt         |  67 --------
>  .../interrupt-controller/mti,gic.yaml         | 152 ++++++++++++++++++
>  2 files changed, 152 insertions(+), 67 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt b/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
> deleted file mode 100644
> index 173595305e26..000000000000
> --- a/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
> +++ /dev/null
> @@ -1,67 +0,0 @@
> -MIPS Global Interrupt Controller (GIC)
> -
> -The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
> -It also supports local (per-processor) interrupts and software-generated
> -interrupts which can be used as IPIs.  The GIC also includes a free-running
> -global timer, per-CPU count/compare timers, and a watchdog.
> -
> -Required properties:
> -- compatible : Should be "mti,gic".
> -- interrupt-controller : Identifies the node as an interrupt controller
> -- #interrupt-cells : Specifies the number of cells needed to encode an
> -  interrupt specifier.  Should be 3.
> -  - The first cell is the type of interrupt, local or shared.
> -    See <include/dt-bindings/interrupt-controller/mips-gic.h>.
> -  - The second cell is the GIC interrupt number.
> -  - The third cell encodes the interrupt flags.
> -    See <include/dt-bindings/interrupt-controller/irq.h> for a list of valid
> -    flags.
> -
> -Optional properties:
> -- reg : Base address and length of the GIC registers.  If not present,
> -  the base address reported by the hardware GCR_GIC_BASE will be used.
> -- mti,reserved-cpu-vectors : Specifies the list of CPU interrupt vectors
> -  to which the GIC may not route interrupts.  Valid values are 2 - 7.
> -  This property is ignored if the CPU is started in EIC mode.
> -- mti,reserved-ipi-vectors : Specifies the range of GIC interrupts that are
> -  reserved for IPIs.
> -  It accepts 2 values, the 1st is the starting interrupt and the 2nd is the size
> -  of the reserved range.
> -  If not specified, the driver will allocate the last 2 * number of VPEs in the
> -  system.
> -
> -Required properties for timer sub-node:
> -- compatible : Should be "mti,gic-timer".
> -- interrupts : Interrupt for the GIC local timer.
> -
> -Optional properties for timer sub-node:
> -- clocks : GIC timer operating clock.
> -- clock-frequency : Clock frequency at which the GIC timers operate.
> -
> -Note that one of clocks or clock-frequency must be specified.
> -
> -Example:
> -
> -	gic: interrupt-controller@1bdc0000 {
> -		compatible = "mti,gic";
> -		reg = <0x1bdc0000 0x20000>;
> -
> -		interrupt-controller;
> -		#interrupt-cells = <3>;
> -
> -		mti,reserved-cpu-vectors = <7>;
> -		mti,reserved-ipi-vectors = <40 8>;
> -
> -		timer {
> -			compatible = "mti,gic-timer";
> -			interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
> -			clock-frequency = <50000000>;
> -		};
> -	};
> -
> -	uart@18101400 {
> -		...
> -		interrupt-parent = <&gic>;
> -		interrupts = <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
> -		...
> -	};
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml b/Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml
> new file mode 100644
> index 000000000000..1e47c0cdc231
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml
> @@ -0,0 +1,152 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

Do you have rights to add BSD?

> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MIPS Global Interrupt Controller
> +
> +maintainers:
> +  - Paul Burton <paulburton@kernel.org>
> +  - Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> +
> +description: |
> +  The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
> +  It also supports local (per-processor) interrupts and software-generated
> +  interrupts which can be used as IPIs. The GIC also includes a free-running
> +  global timer, per-CPU count/compare timers, and a watchdog.
> +
> +allOf:
> +  - $ref: /schemas/interrupt-controller.yaml#

Drop this.

> +
> +properties:
> +  compatible:
> +    const: mti,gic
> +
> +  "#interrupt-cells":
> +    const: 3
> +    description: |
> +      The 1st cell is the type of interrupt: local or shared defined in the
> +      file 'dt-bindings/interrupt-controller/mips-gic.h'. The 2nd cell is the
> +      GIC interrupt number. The 3d cell encodes the interrupt flags setting up
> +      the IRQ trigger modes, which are defined in the file
> +      'dt-bindings/interrupt-controller/irq.h'.
> +
> +  reg:
> +    description: |
> +      Base address and length of the GIC registers space. If not present,
> +      the base address reported by the hardware GCR_GIC_BASE will be used.
> +    maxItems: 1
> +
> +  interrupt-controller: true
> +
> +  mti,reserved-cpu-vectors:
> +    description: |
> +      Specifies the list of CPU interrupt vectors to which the GIC may not
> +      route interrupts. This property is ignored if the CPU is started in EIC
> +      mode.
> +    allOf:
> +      - $ref: /schemas/types.yaml#definitions/uint32-array
> +      - minItems: 1
> +        maxItems: 6
> +        uniqueItems: true
> +        items:
> +          minimum: 2
> +          maximum: 7
> +
> +  mti,reserved-ipi-vectors:
> +    description: |
> +      Specifies the range of GIC interrupts that are reserved for IPIs.
> +      It accepts two values: the 1st is the starting interrupt and the 2nd is
> +      the size of the reserved range. If not specified, the driver will
> +      allocate the last (2 * number of VPEs in the system).
> +    allOf:
> +      - $ref: /schemas/types.yaml#definitions/uint32-array
> +      - items:
> +          - minimum: 0
> +            maximum: 254
> +          - minimum: 2
> +            maximum: 254
> +
> +patternProperties:
> +  "^timer(@[0-9a-f]+)?$":

If you have an unit-address, then there should be a 'reg' property.

Seems like this can be just 'timer'?

> +    type: object
> +    description: |
> +      MIPS GIC includes a free-running global timer, per-CPU count/compare
> +      timers, and a watchdog. Currently only the GIC Timer is supported.
> +    properties:
> +      compatible:
> +        const: mti,gic-timer
> +
> +      interrupts:
> +        description: |
> +          Interrupt for the GIC local timer, so normally it's suppose to be of
> +          <GIC_LOCAL X IRQ_TYPE_NONE> format.
> +        maxItems: 1
> +
> +      clocks:
> +        maxItems: 1
> +
> +      clock-frequency: true
> +
> +    required:
> +      - compatible
> +      - interrupts
> +
> +    oneOf:
> +      - required:
> +          - clocks
> +      - required:
> +          - clock-frequency
> +
> +    additionalProperties: false
> +
> +unevaluatedProperties: false
> +
> +required:
> +  - compatible
> +  - "#interrupt-cells"
> +  - interrupt-controller
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/mips-gic.h>
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +
> +    interrupt-controller@1bdc0000 {
> +      compatible = "mti,gic";
> +      reg = <0x1bdc0000 0x20000>;
> +      interrupt-controller;
> +      #interrupt-cells = <3>;
> +      mti,reserved-cpu-vectors = <7>;
> +      mti,reserved-ipi-vectors = <40 8>;
> +
> +      timer {
> +        compatible = "mti,gic-timer";
> +        interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
> +        clock-frequency = <50000000>;
> +      };
> +    };
> +  - |
> +    #include <dt-bindings/interrupt-controller/mips-gic.h>
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +
> +    interrupt-controller@1bdc0000 {
> +      compatible = "mti,gic";
> +      reg = <0x1bdc0000 0x20000>;
> +      interrupt-controller;
> +      #interrupt-cells = <3>;
> +
> +      timer {
> +        compatible = "mti,gic-timer";
> +        interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
> +        clocks = <&cpu_pll>;
> +      };
> +    };
> +  - |
> +    interrupt-controller {
> +      compatible = "mti,gic";
> +      interrupt-controller;
> +      #interrupt-cells = <3>;
> +    };
> +...
> -- 
> 2.25.1
> 

Re: [PATCH v2 2/6] dt-bindings: interrupt-controller: Convert mti,gic to DT schema

[Sergey Semin]

On Tue, Mar 31, 2020 at 03:02:48PM -0600, Rob Herring wrote:
> On Tue, Mar 24, 2020 at 08:43:21PM +0300, Sergey.Semin@baikalelectronics.ru wrote:
> > From: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> > 
> > Modern device tree bindings are supposed to be created as YAML-files
> > in accordance with DT schema. This commit replaces MIPS GIC legacy bare
> > text binding with YAML file. As before the binding file states that the
> > corresponding dts node is supposed to be compatible with MIPS Global
> > Interrupt Controller indicated by the "mti,gic" compatible string and
> > to provide a mandatory interrupt-controller and '#interrupt-cells'
> > properties. There might be optional registers memory range,
> > "mti,reserved-cpu-vectors" and "mti,reserved-ipi-vectors" properties
> > specified.
> > 
> > MIPS GIC also includes a free-running global timer, per-CPU count/compare
> > timers, and a watchdog. Since currently the GIC Timer is only supported the
> > DT schema expects an IRQ and clock-phandler charged timer sub-node with
> > "mti,mips-gic-timer" compatible string.
> > 
> > Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> > Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> > Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> > Cc: Paul Burton <paulburton@kernel.org>
> > Cc: Ralf Baechle <ralf@linux-mips.org>
> > Cc: Alessandro Zummo <a.zummo@towertech.it>
> > Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
> > Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
> > Cc: Thomas Gleixner <tglx@linutronix.de>
> > Cc: Arnd Bergmann <arnd@arndb.de>
> > Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
> > Cc: Rob Herring <robh+dt@kernel.org>
> > Cc: Mark Rutland <mark.rutland@arm.com>
> > Cc: devicetree@vger.kernel.org
> > Cc: linux-rtc@vger.kernel.org
> > 
> > ---
> > 
> > I don't really know who is the corresponding driver maintainer, so I
> > added to the maintainers schema Paul since he used to be looking for the
> > MIPS arch and Thomas looking after it now. Any idea what email should be
> > specified there instead?
> > 
> > Similarly to the previous patch the "oneOf: - required: ..." pattern isn't
> > working here. Supposedly due to the script' dtschema/lib.py
> > interrupts/interrupts-extended fixup.
> > ---
> >  .../interrupt-controller/mips-gic.txt         |  67 --------
> >  .../interrupt-controller/mti,gic.yaml         | 152 ++++++++++++++++++
> >  2 files changed, 152 insertions(+), 67 deletions(-)
> >  delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
> >  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt b/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
> > deleted file mode 100644
> > index 173595305e26..000000000000
> > --- a/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
> > +++ /dev/null
> > @@ -1,67 +0,0 @@
> > -MIPS Global Interrupt Controller (GIC)
> > -
> > -The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
> > -It also supports local (per-processor) interrupts and software-generated
> > -interrupts which can be used as IPIs.  The GIC also includes a free-running
> > -global timer, per-CPU count/compare timers, and a watchdog.
> > -
> > -Required properties:
> > -- compatible : Should be "mti,gic".
> > -- interrupt-controller : Identifies the node as an interrupt controller
> > -- #interrupt-cells : Specifies the number of cells needed to encode an
> > -  interrupt specifier.  Should be 3.
> > -  - The first cell is the type of interrupt, local or shared.
> > -    See <include/dt-bindings/interrupt-controller/mips-gic.h>.
> > -  - The second cell is the GIC interrupt number.
> > -  - The third cell encodes the interrupt flags.
> > -    See <include/dt-bindings/interrupt-controller/irq.h> for a list of valid
> > -    flags.
> > -
> > -Optional properties:
> > -- reg : Base address and length of the GIC registers.  If not present,
> > -  the base address reported by the hardware GCR_GIC_BASE will be used.
> > -- mti,reserved-cpu-vectors : Specifies the list of CPU interrupt vectors
> > -  to which the GIC may not route interrupts.  Valid values are 2 - 7.
> > -  This property is ignored if the CPU is started in EIC mode.
> > -- mti,reserved-ipi-vectors : Specifies the range of GIC interrupts that are
> > -  reserved for IPIs.
> > -  It accepts 2 values, the 1st is the starting interrupt and the 2nd is the size
> > -  of the reserved range.
> > -  If not specified, the driver will allocate the last 2 * number of VPEs in the
> > -  system.
> > -
> > -Required properties for timer sub-node:
> > -- compatible : Should be "mti,gic-timer".
> > -- interrupts : Interrupt for the GIC local timer.
> > -
> > -Optional properties for timer sub-node:
> > -- clocks : GIC timer operating clock.
> > -- clock-frequency : Clock frequency at which the GIC timers operate.
> > -
> > -Note that one of clocks or clock-frequency must be specified.
> > -
> > -Example:
> > -
> > -	gic: interrupt-controller@1bdc0000 {
> > -		compatible = "mti,gic";
> > -		reg = <0x1bdc0000 0x20000>;
> > -
> > -		interrupt-controller;
> > -		#interrupt-cells = <3>;
> > -
> > -		mti,reserved-cpu-vectors = <7>;
> > -		mti,reserved-ipi-vectors = <40 8>;
> > -
> > -		timer {
> > -			compatible = "mti,gic-timer";
> > -			interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
> > -			clock-frequency = <50000000>;
> > -		};
> > -	};
> > -
> > -	uart@18101400 {
> > -		...
> > -		interrupt-parent = <&gic>;
> > -		interrupts = <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
> > -		...
> > -	};
> > diff --git a/Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml b/Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml
> > new file mode 100644
> > index 000000000000..1e47c0cdc231
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml
> > @@ -0,0 +1,152 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> 
> Do you have rights to add BSD?
> 

My manager said we can submitted the DT schema bindings under both GPL and
BSD licenses. Though I don't know what license was of the legacy binding file.

BTW Rob, you ask about the license very often whether I set pure GPL-2.0
or dual-license header. Just wondering is it some kind of protocol to make
sure a submitter has got proper rights to submit the binding?

> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: MIPS Global Interrupt Controller
> > +
> > +maintainers:
> > +  - Paul Burton <paulburton@kernel.org>
> > +  - Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> > +
> > +description: |
> > +  The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
> > +  It also supports local (per-processor) interrupts and software-generated
> > +  interrupts which can be used as IPIs. The GIC also includes a free-running
> > +  global timer, per-CPU count/compare timers, and a watchdog.
> > +
> > +allOf:
> > +  - $ref: /schemas/interrupt-controller.yaml#
> 
> Drop this.
> 

Ok.

> > +
> > +properties:
> > +  compatible:
> > +    const: mti,gic
> > +
> > +  "#interrupt-cells":
> > +    const: 3
> > +    description: |
> > +      The 1st cell is the type of interrupt: local or shared defined in the
> > +      file 'dt-bindings/interrupt-controller/mips-gic.h'. The 2nd cell is the
> > +      GIC interrupt number. The 3d cell encodes the interrupt flags setting up
> > +      the IRQ trigger modes, which are defined in the file
> > +      'dt-bindings/interrupt-controller/irq.h'.
> > +
> > +  reg:
> > +    description: |
> > +      Base address and length of the GIC registers space. If not present,
> > +      the base address reported by the hardware GCR_GIC_BASE will be used.
> > +    maxItems: 1
> > +
> > +  interrupt-controller: true
> > +
> > +  mti,reserved-cpu-vectors:
> > +    description: |
> > +      Specifies the list of CPU interrupt vectors to which the GIC may not
> > +      route interrupts. This property is ignored if the CPU is started in EIC
> > +      mode.
> > +    allOf:
> > +      - $ref: /schemas/types.yaml#definitions/uint32-array
> > +      - minItems: 1
> > +        maxItems: 6
> > +        uniqueItems: true
> > +        items:
> > +          minimum: 2
> > +          maximum: 7
> > +
> > +  mti,reserved-ipi-vectors:
> > +    description: |
> > +      Specifies the range of GIC interrupts that are reserved for IPIs.
> > +      It accepts two values: the 1st is the starting interrupt and the 2nd is
> > +      the size of the reserved range. If not specified, the driver will
> > +      allocate the last (2 * number of VPEs in the system).
> > +    allOf:
> > +      - $ref: /schemas/types.yaml#definitions/uint32-array
> > +      - items:
> > +          - minimum: 0
> > +            maximum: 254
> > +          - minimum: 2
> > +            maximum: 254
> > +
> > +patternProperties:
> > +  "^timer(@[0-9a-f]+)?$":
> 
> If you have an unit-address, then there should be a 'reg' property.
> 
> Seems like this can be just 'timer'?
> 

Ok. reg property isn't supported by the timer sub-node. So I'll make it to
be just "timer" node with no unit-address number.

-Sergey

> > +    type: object
> > +    description: |
> > +      MIPS GIC includes a free-running global timer, per-CPU count/compare
> > +      timers, and a watchdog. Currently only the GIC Timer is supported.
> > +    properties:
> > +      compatible:
> > +        const: mti,gic-timer
> > +
> > +      interrupts:
> > +        description: |
> > +          Interrupt for the GIC local timer, so normally it's suppose to be of
> > +          <GIC_LOCAL X IRQ_TYPE_NONE> format.
> > +        maxItems: 1
> > +
> > +      clocks:
> > +        maxItems: 1
> > +
> > +      clock-frequency: true
> > +
> > +    required:
> > +      - compatible
> > +      - interrupts
> > +
> > +    oneOf:
> > +      - required:
> > +          - clocks
> > +      - required:
> > +          - clock-frequency
> > +
> > +    additionalProperties: false
> > +
> > +unevaluatedProperties: false
> > +
> > +required:
> > +  - compatible
> > +  - "#interrupt-cells"
> > +  - interrupt-controller
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/interrupt-controller/mips-gic.h>
> > +    #include <dt-bindings/interrupt-controller/irq.h>
> > +
> > +    interrupt-controller@1bdc0000 {
> > +      compatible = "mti,gic";
> > +      reg = <0x1bdc0000 0x20000>;
> > +      interrupt-controller;
> > +      #interrupt-cells = <3>;
> > +      mti,reserved-cpu-vectors = <7>;
> > +      mti,reserved-ipi-vectors = <40 8>;
> > +
> > +      timer {
> > +        compatible = "mti,gic-timer";
> > +        interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
> > +        clock-frequency = <50000000>;
> > +      };
> > +    };
> > +  - |
> > +    #include <dt-bindings/interrupt-controller/mips-gic.h>
> > +    #include <dt-bindings/interrupt-controller/irq.h>
> > +
> > +    interrupt-controller@1bdc0000 {
> > +      compatible = "mti,gic";
> > +      reg = <0x1bdc0000 0x20000>;
> > +      interrupt-controller;
> > +      #interrupt-cells = <3>;
> > +
> > +      timer {
> > +        compatible = "mti,gic-timer";
> > +        interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
> > +        clocks = <&cpu_pll>;
> > +      };
> > +    };
> > +  - |
> > +    interrupt-controller {
> > +      compatible = "mti,gic";
> > +      interrupt-controller;
> > +      #interrupt-cells = <3>;
> > +    };
> > +...
> > -- 
> > 2.25.1
> > 

Re: [PATCH v2 2/6] dt-bindings: interrupt-controller: Convert mti,gic to DT schema

[Rob Herring]

On Wed, Apr 1, 2020 at 4:19 AM Sergey Semin
<Sergey.Semin@baikalelectronics.ru> wrote:
>
> On Tue, Mar 31, 2020 at 03:02:48PM -0600, Rob Herring wrote:
> > On Tue, Mar 24, 2020 at 08:43:21PM +0300, Sergey.Semin@baikalelectronics.ru wrote:
> > > From: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> > >
> > > Modern device tree bindings are supposed to be created as YAML-files
> > > in accordance with DT schema. This commit replaces MIPS GIC legacy bare
> > > text binding with YAML file. As before the binding file states that the
> > > corresponding dts node is supposed to be compatible with MIPS Global
> > > Interrupt Controller indicated by the "mti,gic" compatible string and
> > > to provide a mandatory interrupt-controller and '#interrupt-cells'
> > > properties. There might be optional registers memory range,
> > > "mti,reserved-cpu-vectors" and "mti,reserved-ipi-vectors" properties
> > > specified.
> > >
> > > MIPS GIC also includes a free-running global timer, per-CPU count/compare
> > > timers, and a watchdog. Since currently the GIC Timer is only supported the
> > > DT schema expects an IRQ and clock-phandler charged timer sub-node with
> > > "mti,mips-gic-timer" compatible string.
> > >
> > > Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> > > Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> > > Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> > > Cc: Paul Burton <paulburton@kernel.org>
> > > Cc: Ralf Baechle <ralf@linux-mips.org>
> > > Cc: Alessandro Zummo <a.zummo@towertech.it>
> > > Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
> > > Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
> > > Cc: Thomas Gleixner <tglx@linutronix.de>
> > > Cc: Arnd Bergmann <arnd@arndb.de>
> > > Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
> > > Cc: Rob Herring <robh+dt@kernel.org>
> > > Cc: Mark Rutland <mark.rutland@arm.com>
> > > Cc: devicetree@vger.kernel.org
> > > Cc: linux-rtc@vger.kernel.org
> > >
> > > ---
> > >
> > > I don't really know who is the corresponding driver maintainer, so I
> > > added to the maintainers schema Paul since he used to be looking for the
> > > MIPS arch and Thomas looking after it now. Any idea what email should be
> > > specified there instead?
> > >
> > > Similarly to the previous patch the "oneOf: - required: ..." pattern isn't
> > > working here. Supposedly due to the script' dtschema/lib.py
> > > interrupts/interrupts-extended fixup.
> > > ---
> > >  .../interrupt-controller/mips-gic.txt         |  67 --------
> > >  .../interrupt-controller/mti,gic.yaml         | 152 ++++++++++++++++++
> > >  2 files changed, 152 insertions(+), 67 deletions(-)
> > >  delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
> > >  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml
> > >
> > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt b/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
> > > deleted file mode 100644
> > > index 173595305e26..000000000000
> > > --- a/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
> > > +++ /dev/null
> > > @@ -1,67 +0,0 @@
> > > -MIPS Global Interrupt Controller (GIC)
> > > -
> > > -The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
> > > -It also supports local (per-processor) interrupts and software-generated
> > > -interrupts which can be used as IPIs.  The GIC also includes a free-running
> > > -global timer, per-CPU count/compare timers, and a watchdog.
> > > -
> > > -Required properties:
> > > -- compatible : Should be "mti,gic".
> > > -- interrupt-controller : Identifies the node as an interrupt controller
> > > -- #interrupt-cells : Specifies the number of cells needed to encode an
> > > -  interrupt specifier.  Should be 3.
> > > -  - The first cell is the type of interrupt, local or shared.
> > > -    See <include/dt-bindings/interrupt-controller/mips-gic.h>.
> > > -  - The second cell is the GIC interrupt number.
> > > -  - The third cell encodes the interrupt flags.
> > > -    See <include/dt-bindings/interrupt-controller/irq.h> for a list of valid
> > > -    flags.
> > > -
> > > -Optional properties:
> > > -- reg : Base address and length of the GIC registers.  If not present,
> > > -  the base address reported by the hardware GCR_GIC_BASE will be used.
> > > -- mti,reserved-cpu-vectors : Specifies the list of CPU interrupt vectors
> > > -  to which the GIC may not route interrupts.  Valid values are 2 - 7.
> > > -  This property is ignored if the CPU is started in EIC mode.
> > > -- mti,reserved-ipi-vectors : Specifies the range of GIC interrupts that are
> > > -  reserved for IPIs.
> > > -  It accepts 2 values, the 1st is the starting interrupt and the 2nd is the size
> > > -  of the reserved range.
> > > -  If not specified, the driver will allocate the last 2 * number of VPEs in the
> > > -  system.
> > > -
> > > -Required properties for timer sub-node:
> > > -- compatible : Should be "mti,gic-timer".
> > > -- interrupts : Interrupt for the GIC local timer.
> > > -
> > > -Optional properties for timer sub-node:
> > > -- clocks : GIC timer operating clock.
> > > -- clock-frequency : Clock frequency at which the GIC timers operate.
> > > -
> > > -Note that one of clocks or clock-frequency must be specified.
> > > -
> > > -Example:
> > > -
> > > -   gic: interrupt-controller@1bdc0000 {
> > > -           compatible = "mti,gic";
> > > -           reg = <0x1bdc0000 0x20000>;
> > > -
> > > -           interrupt-controller;
> > > -           #interrupt-cells = <3>;
> > > -
> > > -           mti,reserved-cpu-vectors = <7>;
> > > -           mti,reserved-ipi-vectors = <40 8>;
> > > -
> > > -           timer {
> > > -                   compatible = "mti,gic-timer";
> > > -                   interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
> > > -                   clock-frequency = <50000000>;
> > > -           };
> > > -   };
> > > -
> > > -   uart@18101400 {
> > > -           ...
> > > -           interrupt-parent = <&gic>;
> > > -           interrupts = <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
> > > -           ...
> > > -   };
> > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml b/Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml
> > > new file mode 100644
> > > index 000000000000..1e47c0cdc231
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml
> > > @@ -0,0 +1,152 @@
> > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> >
> > Do you have rights to add BSD?
> >
>
> My manager said we can submitted the DT schema bindings under both GPL and
> BSD licenses. Though I don't know what license was of the legacy binding file.

Anything in the kernel without an explicit license is GPL-2.0-only.

> BTW Rob, you ask about the license very often whether I set pure GPL-2.0
> or dual-license header. Just wondering is it some kind of protocol to make
> sure a submitter has got proper rights to submit the binding?

New bindings should be dual GPL/BSD. Converted bindings should be
relicensed if the authors of the original agree or you should maintain
GPL-2.0-only.

Rob

Re: [PATCH v2 2/6] dt-bindings: interrupt-controller: Convert mti,gic to DT schema

[Sergey Semin]

On Wed, Apr 01, 2020 at 08:13:58AM -0600, Rob Herring wrote:
> On Wed, Apr 1, 2020 at 4:19 AM Sergey Semin
> <Sergey.Semin@baikalelectronics.ru> wrote:
> >
> > On Tue, Mar 31, 2020 at 03:02:48PM -0600, Rob Herring wrote:
> > > On Tue, Mar 24, 2020 at 08:43:21PM +0300, Sergey.Semin@baikalelectronics.ru wrote:
> > > > From: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> > > >
> > > > Modern device tree bindings are supposed to be created as YAML-files
> > > > in accordance with DT schema. This commit replaces MIPS GIC legacy bare
> > > > text binding with YAML file. As before the binding file states that the
> > > > corresponding dts node is supposed to be compatible with MIPS Global
> > > > Interrupt Controller indicated by the "mti,gic" compatible string and
> > > > to provide a mandatory interrupt-controller and '#interrupt-cells'
> > > > properties. There might be optional registers memory range,
> > > > "mti,reserved-cpu-vectors" and "mti,reserved-ipi-vectors" properties
> > > > specified.
> > > >
> > > > MIPS GIC also includes a free-running global timer, per-CPU count/compare
> > > > timers, and a watchdog. Since currently the GIC Timer is only supported the
> > > > DT schema expects an IRQ and clock-phandler charged timer sub-node with
> > > > "mti,mips-gic-timer" compatible string.
> > > >
> > > > Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> > > > Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> > > > Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> > > > Cc: Paul Burton <paulburton@kernel.org>
> > > > Cc: Ralf Baechle <ralf@linux-mips.org>
> > > > Cc: Alessandro Zummo <a.zummo@towertech.it>
> > > > Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
> > > > Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
> > > > Cc: Thomas Gleixner <tglx@linutronix.de>
> > > > Cc: Arnd Bergmann <arnd@arndb.de>
> > > > Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
> > > > Cc: Rob Herring <robh+dt@kernel.org>
> > > > Cc: Mark Rutland <mark.rutland@arm.com>
> > > > Cc: devicetree@vger.kernel.org
> > > > Cc: linux-rtc@vger.kernel.org
> > > >
> > > > ---
> > > >
> > > > I don't really know who is the corresponding driver maintainer, so I
> > > > added to the maintainers schema Paul since he used to be looking for the
> > > > MIPS arch and Thomas looking after it now. Any idea what email should be
> > > > specified there instead?
> > > >
> > > > Similarly to the previous patch the "oneOf: - required: ..." pattern isn't
> > > > working here. Supposedly due to the script' dtschema/lib.py
> > > > interrupts/interrupts-extended fixup.
> > > > ---
> > > >  .../interrupt-controller/mips-gic.txt         |  67 --------
> > > >  .../interrupt-controller/mti,gic.yaml         | 152 ++++++++++++++++++
> > > >  2 files changed, 152 insertions(+), 67 deletions(-)
> > > >  delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
> > > >  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt b/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
> > > > deleted file mode 100644
> > > > index 173595305e26..000000000000
> > > > --- a/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
> > > > +++ /dev/null
> > > > @@ -1,67 +0,0 @@
> > > > -MIPS Global Interrupt Controller (GIC)
> > > > -
> > > > -The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
> > > > -It also supports local (per-processor) interrupts and software-generated
> > > > -interrupts which can be used as IPIs.  The GIC also includes a free-running
> > > > -global timer, per-CPU count/compare timers, and a watchdog.
> > > > -
> > > > -Required properties:
> > > > -- compatible : Should be "mti,gic".
> > > > -- interrupt-controller : Identifies the node as an interrupt controller
> > > > -- #interrupt-cells : Specifies the number of cells needed to encode an
> > > > -  interrupt specifier.  Should be 3.
> > > > -  - The first cell is the type of interrupt, local or shared.
> > > > -    See <include/dt-bindings/interrupt-controller/mips-gic.h>.
> > > > -  - The second cell is the GIC interrupt number.
> > > > -  - The third cell encodes the interrupt flags.
> > > > -    See <include/dt-bindings/interrupt-controller/irq.h> for a list of valid
> > > > -    flags.
> > > > -
> > > > -Optional properties:
> > > > -- reg : Base address and length of the GIC registers.  If not present,
> > > > -  the base address reported by the hardware GCR_GIC_BASE will be used.
> > > > -- mti,reserved-cpu-vectors : Specifies the list of CPU interrupt vectors
> > > > -  to which the GIC may not route interrupts.  Valid values are 2 - 7.
> > > > -  This property is ignored if the CPU is started in EIC mode.
> > > > -- mti,reserved-ipi-vectors : Specifies the range of GIC interrupts that are
> > > > -  reserved for IPIs.
> > > > -  It accepts 2 values, the 1st is the starting interrupt and the 2nd is the size
> > > > -  of the reserved range.
> > > > -  If not specified, the driver will allocate the last 2 * number of VPEs in the
> > > > -  system.
> > > > -
> > > > -Required properties for timer sub-node:
> > > > -- compatible : Should be "mti,gic-timer".
> > > > -- interrupts : Interrupt for the GIC local timer.
> > > > -
> > > > -Optional properties for timer sub-node:
> > > > -- clocks : GIC timer operating clock.
> > > > -- clock-frequency : Clock frequency at which the GIC timers operate.
> > > > -
> > > > -Note that one of clocks or clock-frequency must be specified.
> > > > -
> > > > -Example:
> > > > -
> > > > -   gic: interrupt-controller@1bdc0000 {
> > > > -           compatible = "mti,gic";
> > > > -           reg = <0x1bdc0000 0x20000>;
> > > > -
> > > > -           interrupt-controller;
> > > > -           #interrupt-cells = <3>;
> > > > -
> > > > -           mti,reserved-cpu-vectors = <7>;
> > > > -           mti,reserved-ipi-vectors = <40 8>;
> > > > -
> > > > -           timer {
> > > > -                   compatible = "mti,gic-timer";
> > > > -                   interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
> > > > -                   clock-frequency = <50000000>;
> > > > -           };
> > > > -   };
> > > > -
> > > > -   uart@18101400 {
> > > > -           ...
> > > > -           interrupt-parent = <&gic>;
> > > > -           interrupts = <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
> > > > -           ...
> > > > -   };
> > > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml b/Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml
> > > > new file mode 100644
> > > > index 000000000000..1e47c0cdc231
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml
> > > > @@ -0,0 +1,152 @@
> > > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > >
> > > Do you have rights to add BSD?
> > >
> >
> > My manager said we can submitted the DT schema bindings under both GPL and
> > BSD licenses. Though I don't know what license was of the legacy binding file.
> 
> Anything in the kernel without an explicit license is GPL-2.0-only.
> 
> > BTW Rob, you ask about the license very often whether I set pure GPL-2.0
> > or dual-license header. Just wondering is it some kind of protocol to make
> > sure a submitter has got proper rights to submit the binding?
> 
> New bindings should be dual GPL/BSD. Converted bindings should be
> relicensed if the authors of the original agree or you should maintain
> GPL-2.0-only.
> 
> Rob

Ah. ok. I didn't know that the legacy bindings have GPL-2.0 license by
default. Thanks. I'll keep it in mind in patchsets with bindings conversion.

Regards,
-Sergey

[PATCH v2 3/6] clocksource: dw_apb_timer: Set clockevent any-possible-CPU mask

[Sergey.Semin]

From: Serge Semin <Sergey.Semin@baikalelectronics.ru>

Currently the DW APB Timer driver binds all clockevent timers to
CPU #0. This isn't good for multiple reasons. First of all seeing
the device is placed on APB bus (which makes it accessible from any
CPU core), accessible over MMIO and having the DYNIRQ flag set we
can be sure that manually binding the timer to any CPU just isn't
correct. By doing so we just set an extra limitation on device usage.
This also doesn't reflect the device actual capability, since by
setting the IRQ affinity we can make it virtually local to any CPU.
Secondly imagine if you had a real CPU-local timer with the same
rating and the same CPU-affinity. In this case if DW APB timer was
registered first, then due to the clockevent framework tick-timer
selection procedure we'll end up with the real CPU-local timer being
left unselected for clock-events tracking. But on most of the platforms
(MIPS/ARM/etc) such timers are normally embedded into the CPU core and
are accessible with much better performance then devices placed on APB.
For instance in MIPS architectures there is r4k-timer, which is
CPU-local, assigned with the same rating, and normally its
clockevent device is registered after the platform-specific one.

So in order to fix all of these issues lets set the DW APB clockevent
timer cpumask to be 'cpu_possible_mask'. By doing so the clockevent
framework would prefer to select the real CPU-local timer instead
of DW APB one. Otherwise if there is no other than DW APB device for
clockevents tracking then it will be selected.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
---
 drivers/clocksource/dw_apb_timer.c    | 18 +++++++-----------
 drivers/clocksource/dw_apb_timer_of.c |  3 +--
 include/linux/dw_apb_timer.h          |  2 +-
 3 files changed, 9 insertions(+), 14 deletions(-)

diff --git a/drivers/clocksource/dw_apb_timer.c b/drivers/clocksource/dw_apb_timer.c
index 654766538f93..f213bcb4cf71 100644
--- a/drivers/clocksource/dw_apb_timer.c
+++ b/drivers/clocksource/dw_apb_timer.c
@@ -106,6 +106,7 @@ static irqreturn_t dw_apb_clockevent_irq(int irq, void *data)
 		dw_ced->eoi(&dw_ced->timer);
 
 	evt->event_handler(evt);
+
 	return IRQ_HANDLED;
 }
 
@@ -123,8 +124,7 @@ static int apbt_shutdown(struct clock_event_device *evt)
 	struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
 	u32 ctrl;
 
-	pr_debug("%s CPU %d state=shutdown\n", __func__,
-		 cpumask_first(evt->cpumask));
+	pr_debug("%s state=shutdown\n", __func__);
 
 	ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
 	ctrl &= ~APBTMR_CONTROL_ENABLE;
@@ -137,8 +137,7 @@ static int apbt_set_oneshot(struct clock_event_device *evt)
 	struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
 	u32 ctrl;
 
-	pr_debug("%s CPU %d state=oneshot\n", __func__,
-		 cpumask_first(evt->cpumask));
+	pr_debug("%s state=oneshot\n", __func__);
 
 	ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
 	/*
@@ -170,8 +169,7 @@ static int apbt_set_periodic(struct clock_event_device *evt)
 	unsigned long period = DIV_ROUND_UP(dw_ced->timer.freq, HZ);
 	u32 ctrl;
 
-	pr_debug("%s CPU %d state=periodic\n", __func__,
-		 cpumask_first(evt->cpumask));
+	pr_debug("%s state=periodic\n", __func__);
 
 	ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
 	ctrl |= APBTMR_CONTROL_MODE_PERIODIC;
@@ -194,8 +192,7 @@ static int apbt_resume(struct clock_event_device *evt)
 {
 	struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
 
-	pr_debug("%s CPU %d state=resume\n", __func__,
-		 cpumask_first(evt->cpumask));
+	pr_debug("%s state=resume\n", __func__);
 
 	apbt_enable_int(&dw_ced->timer);
 	return 0;
@@ -222,7 +219,6 @@ static int apbt_next_event(unsigned long delta,
 /**
  * dw_apb_clockevent_init() - use an APB timer as a clock_event_device
  *
- * @cpu:	The CPU the events will be targeted at.
  * @name:	The name used for the timer and the IRQ for it.
  * @rating:	The rating to give the timer.
  * @base:	I/O base for the timer registers.
@@ -237,7 +233,7 @@ static int apbt_next_event(unsigned long delta,
  * releasing the IRQ.
  */
 struct dw_apb_clock_event_device *
-dw_apb_clockevent_init(int cpu, const char *name, unsigned rating,
+dw_apb_clockevent_init(const char *name, unsigned int rating,
 		       void __iomem *base, int irq, unsigned long freq)
 {
 	struct dw_apb_clock_event_device *dw_ced =
@@ -257,7 +253,7 @@ dw_apb_clockevent_init(int cpu, const char *name, unsigned rating,
 	dw_ced->ced.max_delta_ticks = 0x7fffffff;
 	dw_ced->ced.min_delta_ns = clockevent_delta2ns(5000, &dw_ced->ced);
 	dw_ced->ced.min_delta_ticks = 5000;
-	dw_ced->ced.cpumask = cpumask_of(cpu);
+	dw_ced->ced.cpumask = cpu_possible_mask;
 	dw_ced->ced.features = CLOCK_EVT_FEAT_PERIODIC |
 				CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_DYNIRQ;
 	dw_ced->ced.set_state_shutdown = apbt_shutdown;
diff --git a/drivers/clocksource/dw_apb_timer_of.c b/drivers/clocksource/dw_apb_timer_of.c
index 8c28b127759f..0a2505b323d7 100644
--- a/drivers/clocksource/dw_apb_timer_of.c
+++ b/drivers/clocksource/dw_apb_timer_of.c
@@ -73,8 +73,7 @@ static void __init add_clockevent(struct device_node *event_timer)
 
 	timer_get_base_and_rate(event_timer, &iobase, &rate);
 
-	ced = dw_apb_clockevent_init(0, event_timer->name, 300, iobase, irq,
-				     rate);
+	ced = dw_apb_clockevent_init(event_timer->name, 300, iobase, irq, rate);
 	if (!ced)
 		panic("Unable to initialise clockevent device");
 
diff --git a/include/linux/dw_apb_timer.h b/include/linux/dw_apb_timer.h
index 14f072edbca5..2f3597a199bb 100644
--- a/include/linux/dw_apb_timer.h
+++ b/include/linux/dw_apb_timer.h
@@ -40,7 +40,7 @@ void dw_apb_clockevent_resume(struct dw_apb_clock_event_device *dw_ced);
 void dw_apb_clockevent_stop(struct dw_apb_clock_event_device *dw_ced);
 
 struct dw_apb_clock_event_device *
-dw_apb_clockevent_init(int cpu, const char *name, unsigned rating,
+dw_apb_clockevent_init(const char *name, unsigned int rating,
 		       void __iomem *base, int irq, unsigned long freq);
 struct dw_apb_clocksource *
 dw_apb_clocksource_init(unsigned rating, const char *name, void __iomem *base,
-- 
2.25.1

[PATCH v2 4/6] clocksource: dw_apb_timer_of: Fix missing clockevent timers

[Sergey.Semin]

From: Serge Semin <Sergey.Semin@baikalelectronics.ru>

Commit 100214889973 ("clocksource: dw_apb_timer_of: use
clocksource_of_init") replaced a publicly available driver
initialization method with one called by the timer_probe() method
available after CLKSRC_OF. In current implementation it traverses
all the timers available in the system and calls their initialization
methods if corresponding devices were either in dtb or in acpi. But
if before the commit any number of available timers would be installed
as clockevent and clocksource devices, after that there would be at most
two. The rest are just ignored since default case branch doesn't do
anything. I don't see a reason of such behaviour, neither the commit
message explains it. Moreover this might be wrong if on some platforms
these timers might be used for different purpose, as virtually CPU-local
clockevent timers and as an independent broadcast timer. So in order
to keep the compatibility with the platforms where the order of the
timers detection has some meaning, lets add the secondly discovered
timer to be of clocksource/sched_clock type, while the very first and
the others would provide the clockevents service.

Fixes: 100214889973 ("clocksource: dw_apb_timer_of: use clocksource_of_init")
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
---
 drivers/clocksource/dw_apb_timer_of.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/clocksource/dw_apb_timer_of.c b/drivers/clocksource/dw_apb_timer_of.c
index 0a2505b323d7..0b61b90a525e 100644
--- a/drivers/clocksource/dw_apb_timer_of.c
+++ b/drivers/clocksource/dw_apb_timer_of.c
@@ -146,10 +146,6 @@ static int num_called;
 static int __init dw_apb_timer_init(struct device_node *timer)
 {
 	switch (num_called) {
-	case 0:
-		pr_debug("%s: found clockevent timer\n", __func__);
-		add_clockevent(timer);
-		break;
 	case 1:
 		pr_debug("%s: found clocksource timer\n", __func__);
 		add_clocksource(timer);
@@ -160,6 +156,8 @@ static int __init dw_apb_timer_init(struct device_node *timer)
 #endif
 		break;
 	default:
+		pr_debug("%s: found clockevent timer\n", __func__);
+		add_clockevent(timer);
 		break;
 	}
 
-- 
2.25.1

[PATCH v2 5/6] clocksource: mips-gic-timer: Register as sched_clock

[Sergey.Semin]

From: Paul Burton <paulburton@kernel.org>

The MIPS GIC timer is well suited for use as sched_clock, so register it
as such.

Whilst the existing gic_read_count() function matches the prototype
needed by sched_clock_register() already, we split it into 2 functions
in order to remove the need to evaluate the mips_cm_is64 condition
within each call since sched_clock should be as fast as possible.

Signed-off-by: Paul Burton <paulburton@kernel.org>
Cc: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
---
 drivers/clocksource/mips-gic-timer.c | 23 +++++++++++++++++++----
 1 file changed, 19 insertions(+), 4 deletions(-)

diff --git a/drivers/clocksource/mips-gic-timer.c b/drivers/clocksource/mips-gic-timer.c
index 37671a5d4ed9..8239ff99cfe4 100644
--- a/drivers/clocksource/mips-gic-timer.c
+++ b/drivers/clocksource/mips-gic-timer.c
@@ -16,6 +16,7 @@
 #include <linux/notifier.h>
 #include <linux/of_irq.h>
 #include <linux/percpu.h>
+#include <linux/sched_clock.h>
 #include <linux/smp.h>
 #include <linux/time.h>
 #include <asm/mips-cps.h>
@@ -24,13 +25,10 @@ static DEFINE_PER_CPU(struct clock_event_device, gic_clockevent_device);
 static int gic_timer_irq;
 static unsigned int gic_frequency;
 
-static u64 notrace gic_read_count(void)
+static u64 notrace gic_read_count_2x32(void)
 {
 	unsigned int hi, hi2, lo;
 
-	if (mips_cm_is64)
-		return read_gic_counter();
-
 	do {
 		hi = read_gic_counter_32h();
 		lo = read_gic_counter_32l();
@@ -40,6 +38,19 @@ static u64 notrace gic_read_count(void)
 	return (((u64) hi) << 32) + lo;
 }
 
+static u64 notrace gic_read_count_64(void)
+{
+	return read_gic_counter();
+}
+
+static u64 notrace gic_read_count(void)
+{
+	if (mips_cm_is64)
+		return gic_read_count_64();
+
+	return gic_read_count_2x32();
+}
+
 static int gic_next_event(unsigned long delta, struct clock_event_device *evt)
 {
 	int cpu = cpumask_first(evt->cpumask);
@@ -228,6 +239,10 @@ static int __init gic_clocksource_of_init(struct device_node *node)
 	/* And finally start the counter */
 	clear_gic_config(GIC_CONFIG_COUNTSTOP);
 
+	sched_clock_register(mips_cm_is64 ?
+			     gic_read_count_64 : gic_read_count_2x32,
+			     64, gic_frequency);
+
 	return 0;
 }
 TIMER_OF_DECLARE(mips_gic_timer, "mti,gic-timer",
-- 
2.25.1

[PATCH v2 6/6] clocksource: mips-gic-timer: Set limitations on clocksource/sched-clocks usage

[Sergey.Semin]

From: Serge Semin <Sergey.Semin@baikalelectronics.ru>

Currently neither clocksource nor scheduler clock kernel framework
support the clocks with variable frequency. Needless to say how many
problems may cause the sudden base clocks frequency change. In a
simplest case the system time will either slow down or speed up.
Since on CM2.5 and earlier MIPS GIC timer is synchronously clocked
with CPU we must set some limitations on using it for these frameworks
if CPU frequency may change. First of all it's not safe to have the
MIPS GIC used for scheduler timings. So we shouldn't proceed with
the clocks registration in the sched-subsystem. Secondly we must
significantly decrease the MIPS GIC clocksource rating. This will let
the system to use it only as a last resort.

Note CM3.x-based systems may also experience the problems with MIPS GIC
if the CPU-frequency change is activated for the whole CPU cluster
instead of using the individual CPC core clocks divider.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
---
 drivers/clocksource/mips-gic-timer.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/clocksource/mips-gic-timer.c b/drivers/clocksource/mips-gic-timer.c
index 8239ff99cfe4..5eb241b8b28d 100644
--- a/drivers/clocksource/mips-gic-timer.c
+++ b/drivers/clocksource/mips-gic-timer.c
@@ -185,7 +185,10 @@ static int __init __gic_clocksource_init(void)
 	gic_clocksource.mask = CLOCKSOURCE_MASK(count_width);
 
 	/* Calculate a somewhat reasonable rating value. */
-	gic_clocksource.rating = 200 + gic_frequency / 10000000;
+	if (mips_cm_revision() >= CM_REV_CM3 || !IS_ENABLED(CONFIG_CPU_FREQ))
+		gic_clocksource.rating = 200 + gic_frequency / 10000000;
+	else
+		gic_clocksource.rating = 99;
 
 	ret = clocksource_register_hz(&gic_clocksource, gic_frequency);
 	if (ret < 0)
@@ -239,9 +242,11 @@ static int __init gic_clocksource_of_init(struct device_node *node)
 	/* And finally start the counter */
 	clear_gic_config(GIC_CONFIG_COUNTSTOP);
 
-	sched_clock_register(mips_cm_is64 ?
-			     gic_read_count_64 : gic_read_count_2x32,
-			     64, gic_frequency);
+	if (mips_cm_revision() >= CM_REV_CM3 || !IS_ENABLED(CONFIG_CPU_FREQ)) {
+		sched_clock_register(mips_cm_is64 ?
+				     gic_read_count_64 : gic_read_count_2x32,
+				     64, gic_frequency);
+	}
 
 	return 0;
 }
-- 
2.25.1

[PATCH v3 0/7] clocksource: Fix MIPS GIC and DW APB Timer for Baikal-T1 SoC support

[Serge Semin]

From: Serge Semin <fancer.lancer@gmail.com>

As for all Baikal-T1 SoC related patchsets, which need this, we replaced
the DW APB Timer legacy plain text-based dt-binding file with DT schema.
Similarly the MIPS GIC bindings file is also converted to DT schema seeing
it also defines the MIPS GIC Timer binding.

Aside from MIPS-specific r4k timer Baikal-T1 chip also provides a
functionality of two another timers: embedded into the MIPS GIC timer and
three external DW timers available over APB bus. But we can't use them
before the corresponding drivers are properly fixed. First of all DW APB
Timer shouldn't be bound to a single CPU, since as being accessible over
APB they are external with respect to all possible CPUs. Secondly there
might be more than just two DW APB Timers in the system (Baikal-T1 has
three of them), so permit the driver to use one of them as a clocksource
and the rest - for clockevents. Thirdly it's possible to use MIPS GIC
timer as a clocksource so register it in the corresponding subsystem
(the patch has been found in the Paul Burton MIPS repo so I left the
original Signed-off-by attribute). Finally in the same way as r4k timer
the MIPS GIC timer should be used with care when CPUFREQ config is enabled
since in case of CM2 the timer counting depends on the CPU reference clock
frequency while the clocksource subsystem currently doesn't support the
timers with non-stable clock.

This patchset is rebased and tested on the mainline Linux kernel 5.7-rc4:
0e698dfa2822 ("Linux 5.7-rc4")
tag: v5.7-rc4

Changelog v2:
- Fix the SoB tags.
- Our corporate email server doesn't change Message-Id anymore, so the
  patchset is resubmitted being in the cover-letter-threaded format.
- Convert the "snps,dw-apb-timer" binding to DT schema in a dedicated
  patch.
- Convert the "mti,gic" binding to DT schema in a dedicated patch.

Changelog v3:
- Make the MIPS GIC timer sub-node name not having a unit-address number.
- Discard allOf: [ $ref: /schemas/interrupt-controller.yaml# ] from MIPS
  GIC bindings.
- Add patch moving the "snps,dw-apb-timer" binding file to the directory
  with timers binding files.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Maxim Kaurkin <Maxim.Kaurkin@baikalelectronics.ru>
Cc: Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>
Cc: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Cc: Ekaterina Skachko <Ekaterina.Skachko@baikalelectronics.ru>
Cc: Vadim Vlasov <V.Vlasov@baikalelectronics.ru>
Cc: Alexey Kolotnikov <Alexey.Kolotnikov@baikalelectronics.ru>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Alessandro Zummo <a.zummo@towertech.it>
Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: linux-rtc@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org

Paul Burton (1):
  clocksource: mips-gic-timer: Register as sched_clock

Serge Semin (6):
  dt-bindings: rtc: Convert snps,dw-apb-timer to DT schema
  dt-bindings: timer: Move snps,dw-apb-timer DT schema from rtc
  dt-bindings: interrupt-controller: Convert mti,gic to DT schema
  clocksource: dw_apb_timer: Set clockevent any-possible-CPU mask
  clocksource: dw_apb_timer_of: Fix missing clockevent timers
  clocksource: mips-gic-timer: Set limitations on
    clocksource/sched-clocks usage

 .../interrupt-controller/mips-gic.txt         |  67 --------
 .../interrupt-controller/mti,gic.yaml         | 148 ++++++++++++++++++
 .../devicetree/bindings/rtc/dw-apb.txt        |  32 ----
 .../bindings/timer/snps,dw-apb-timer.yaml     |  88 +++++++++++
 drivers/clocksource/dw_apb_timer.c            |  18 +--
 drivers/clocksource/dw_apb_timer_of.c         |   9 +-
 drivers/clocksource/mips-gic-timer.c          |  30 +++-
 include/linux/dw_apb_timer.h                  |   2 +-
 8 files changed, 272 insertions(+), 122 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml
 delete mode 100644 Documentation/devicetree/bindings/rtc/dw-apb.txt
 create mode 100644 Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml

-- 
2.25.1

[PATCH v3 1/7] dt-bindings: rtc: Convert snps,dw-apb-timer to DT schema

[Serge Semin]

Modern device tree bindings are supposed to be created as YAML-files
in accordance with DT schema. This commit replaces Synopsys DW Timer
legacy bare text binding with YAML file. As before the binding file
states that the corresponding dts node is supposed to be compatible
with generic DW APB Timer indicated by the "snps,dw-apb-timer"
compatible string and to provide a mandatory registers memory range,
one timer interrupt, either reference clock source or a fixed clock
rate value. It may also have an optional APB bus reference clock
phandle specified.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Rob Herring <robh@kernel.org>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: linux-mips@vger.kernel.org

---

This binding file doesn't belong to the bindings/rtc seeing it's a pure
timer with no rtc facilities like days/months/years counting and alarms.
The binding file will be moved to the
"Documentation/devicetree/bindings/timer/" directory in the next patch.

I also don't know who is the corresponding driver maintainer, so I added
Daniel Lezcano to the maintainers schema. Any idea what email should be
specified there instead?

Changelog v3:
- Since it's a conversion patch use GPL-2.0-only SPDX header.
- Replace "additionalProperties: false" property with
  "unevaluatedProperties: false".
---
 .../devicetree/bindings/rtc/dw-apb.txt        | 32 -------
 .../bindings/rtc/snps,dw-apb-timer.yaml       | 88 +++++++++++++++++++
 2 files changed, 88 insertions(+), 32 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/rtc/dw-apb.txt
 create mode 100644 Documentation/devicetree/bindings/rtc/snps,dw-apb-timer.yaml

diff --git a/Documentation/devicetree/bindings/rtc/dw-apb.txt b/Documentation/devicetree/bindings/rtc/dw-apb.txt
deleted file mode 100644
index c703d51abb6c..000000000000
--- a/Documentation/devicetree/bindings/rtc/dw-apb.txt
+++ /dev/null
@@ -1,32 +0,0 @@
-* Designware APB timer
-
-Required properties:
-- compatible: One of:
- 	"snps,dw-apb-timer"
-	"snps,dw-apb-timer-sp" <DEPRECATED>
-	"snps,dw-apb-timer-osc" <DEPRECATED>
-- reg: physical base address of the controller and length of memory mapped
-  region.
-- interrupts: IRQ line for the timer.
-- either clocks+clock-names or clock-frequency properties
-
-Optional properties:
-- clocks	: list of clock specifiers, corresponding to entries in
-		  the clock-names property;
-- clock-names	: should contain "timer" and "pclk" entries, matching entries
-		  in the clocks property.
-- clock-frequency: The frequency in HZ of the timer.
-- clock-freq: For backwards compatibility with picoxcell
-
-If using the clock specifiers, the pclk clock is optional, as not all
-systems may use one.
-
-
-Example:
-	timer@ffe00000 {
-		compatible = "snps,dw-apb-timer";
-		interrupts = <0 170 4>;
-		reg = <0xffe00000 0x1000>;
-		clocks = <&timer_clk>, <&timer_pclk>;
-		clock-names = "timer", "pclk";
-	};
diff --git a/Documentation/devicetree/bindings/rtc/snps,dw-apb-timer.yaml b/Documentation/devicetree/bindings/rtc/snps,dw-apb-timer.yaml
new file mode 100644
index 000000000000..002fe1ee709b
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/snps,dw-apb-timer.yaml
@@ -0,0 +1,88 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rtc/snps,dw-apb-timer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synopsys DesignWare APB Timer
+
+maintainers:
+  - Daniel Lezcano <daniel.lezcano@linaro.org>
+
+properties:
+  compatible:
+    oneOf:
+      - const: snps,dw-apb-timer
+      - enum:
+          - snps,dw-apb-timer-sp
+          - snps,dw-apb-timer-osc
+        deprecated: true
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    minItems: 1
+    items:
+       - description: Timer ticks reference clock source
+       - description: APB interface clock source
+
+  clock-names:
+    minItems: 1
+    items:
+      - const: timer
+      - const: pclk
+
+  clock-frequency: true
+
+  clock-freq:
+    $ref: "/schemas/types.yaml#/definitions/uint32"
+    description: |
+      Has the same meaning as the 'clock-frequency' property - timer clock
+      frequency in HZ, but is defined only for the backwards compatibility
+      with the picoxcell platform.
+
+unevaluatedProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+oneOf:
+  - required:
+      - clocks
+      - clock-names
+  - required:
+      - clock-frequency
+  - required:
+      - clock-freq
+
+examples:
+  - |
+    timer@ffe00000 {
+      compatible = "snps,dw-apb-timer";
+      interrupts = <0 170 4>;
+      reg = <0xffe00000 0x1000>;
+      clocks = <&timer_clk>, <&timer_pclk>;
+      clock-names = "timer", "pclk";
+    };
+  - |
+    timer@ffe00000 {
+      compatible = "snps,dw-apb-timer";
+      interrupts = <0 170 4>;
+      reg = <0xffe00000 0x1000>;
+      clocks = <&timer_clk>;
+      clock-names = "timer";
+    };
+  - |
+    timer@ffe00000 {
+      compatible = "snps,dw-apb-timer";
+      interrupts = <0 170 4>;
+      reg = <0xffe00000 0x1000>;
+      clock-frequency = <25000000>;
+    };
+...
-- 
2.25.1

[PATCH v3 2/7] dt-bindings: timer: Move snps,dw-apb-timer DT schema from rtc

[Serge Semin]

This binding file doesn't belong to the rtc seeing it's a pure timer
with no rtc facilities like days/months/years counting and alarms.
So move the YAML-file to the Documentation/devicetree/bindings/timer/
directory.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: linux-mips@vger.kernel.org
---
 .../devicetree/bindings/{rtc => timer}/snps,dw-apb-timer.yaml   | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
 rename Documentation/devicetree/bindings/{rtc => timer}/snps,dw-apb-timer.yaml (96%)

diff --git a/Documentation/devicetree/bindings/rtc/snps,dw-apb-timer.yaml b/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
similarity index 96%
rename from Documentation/devicetree/bindings/rtc/snps,dw-apb-timer.yaml
rename to Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
index 002fe1ee709b..5d300efdf0ca 100644
--- a/Documentation/devicetree/bindings/rtc/snps,dw-apb-timer.yaml
+++ b/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-only
 %YAML 1.2
 ---
-$id: http://devicetree.org/schemas/rtc/snps,dw-apb-timer.yaml#
+$id: http://devicetree.org/schemas/timer/snps,dw-apb-timer.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
 title: Synopsys DesignWare APB Timer
-- 
2.25.1

Re: [PATCH v3 2/7] dt-bindings: timer: Move snps,dw-apb-timer DT schema from rtc

[Alexandre Belloni]

On 07/05/2020 00:41:02+0300, Serge Semin wrote:
> This binding file doesn't belong to the rtc seeing it's a pure timer
> with no rtc facilities like days/months/years counting and alarms.
> So move the YAML-file to the Documentation/devicetree/bindings/timer/
> directory.
> 
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: Paul Burton <paulburton@kernel.org>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: linux-mips@vger.kernel.org
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>

> ---
>  .../devicetree/bindings/{rtc => timer}/snps,dw-apb-timer.yaml   | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>  rename Documentation/devicetree/bindings/{rtc => timer}/snps,dw-apb-timer.yaml (96%)
> 
> diff --git a/Documentation/devicetree/bindings/rtc/snps,dw-apb-timer.yaml b/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
> similarity index 96%
> rename from Documentation/devicetree/bindings/rtc/snps,dw-apb-timer.yaml
> rename to Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
> index 002fe1ee709b..5d300efdf0ca 100644
> --- a/Documentation/devicetree/bindings/rtc/snps,dw-apb-timer.yaml
> +++ b/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
> @@ -1,7 +1,7 @@
>  # SPDX-License-Identifier: GPL-2.0-only
>  %YAML 1.2
>  ---
> -$id: http://devicetree.org/schemas/rtc/snps,dw-apb-timer.yaml#
> +$id: http://devicetree.org/schemas/timer/snps,dw-apb-timer.yaml#
>  $schema: http://devicetree.org/meta-schemas/core.yaml#
>  
>  title: Synopsys DesignWare APB Timer
> -- 
> 2.25.1
> 

-- 
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

Re: [PATCH v3 2/7] dt-bindings: timer: Move snps,dw-apb-timer DT schema from rtc

[Rob Herring]

On Thu, 7 May 2020 00:41:02 +0300, Serge Semin wrote:
> This binding file doesn't belong to the rtc seeing it's a pure timer
> with no rtc facilities like days/months/years counting and alarms.
> So move the YAML-file to the Documentation/devicetree/bindings/timer/
> directory.
> 
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: Paul Burton <paulburton@kernel.org>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: linux-mips@vger.kernel.org
> ---
>  .../devicetree/bindings/{rtc => timer}/snps,dw-apb-timer.yaml   | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>  rename Documentation/devicetree/bindings/{rtc => timer}/snps,dw-apb-timer.yaml (96%)
> 

Acked-by: Rob Herring <robh@kernel.org>

[PATCH v3 3/7] dt-bindings: interrupt-controller: Convert mti,gic to DT schema

[Serge Semin]

Modern device tree bindings are supposed to be created as YAML-files
in accordance with DT schema. This commit replaces MIPS GIC legacy bare
text binding with YAML file. As before the binding file states that the
corresponding dts node is supposed to be compatible with MIPS Global
Interrupt Controller indicated by the "mti,gic" compatible string and
to provide a mandatory interrupt-controller and '#interrupt-cells'
properties. There might be optional registers memory range,
"mti,reserved-cpu-vectors" and "mti,reserved-ipi-vectors" properties
specified.

MIPS GIC also includes a free-running global timer, per-CPU count/compare
timers, and a watchdog. Since currently the GIC Timer is only supported the
DT schema expects an IRQ and clock-phandler charged timer sub-node with
"mti,mips-gic-timer" compatible string.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Alessandro Zummo <a.zummo@towertech.it>
Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: linux-mips@vger.kernel.org
Cc: linux-rtc@vger.kernel.org

---

I don't really know who is the corresponding driver maintainer, so I
added Paul to the maintainers property since he used to be looking for the
MIPS arch and Thomas looking after it now. Any idea what email should be
specified there instead?

Changelog v3:
- Since timer sub-node has no unit-address, the node shouldn't be named
  with one. So alter the MIPS GIC bindings to have a pure "timer"
  sub-node.
- Discard allOf: [ $ref: /schemas/interrupt-controller.yaml# ].
- Since it's a conversion patch use GPL-2.0-only SPDX header.
---
 .../interrupt-controller/mips-gic.txt         |  67 --------
 .../interrupt-controller/mti,gic.yaml         | 148 ++++++++++++++++++
 2 files changed, 148 insertions(+), 67 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml

diff --git a/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt b/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
deleted file mode 100644
index 173595305e26..000000000000
--- a/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
+++ /dev/null
@@ -1,67 +0,0 @@
-MIPS Global Interrupt Controller (GIC)
-
-The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
-It also supports local (per-processor) interrupts and software-generated
-interrupts which can be used as IPIs.  The GIC also includes a free-running
-global timer, per-CPU count/compare timers, and a watchdog.
-
-Required properties:
-- compatible : Should be "mti,gic".
-- interrupt-controller : Identifies the node as an interrupt controller
-- #interrupt-cells : Specifies the number of cells needed to encode an
-  interrupt specifier.  Should be 3.
-  - The first cell is the type of interrupt, local or shared.
-    See <include/dt-bindings/interrupt-controller/mips-gic.h>.
-  - The second cell is the GIC interrupt number.
-  - The third cell encodes the interrupt flags.
-    See <include/dt-bindings/interrupt-controller/irq.h> for a list of valid
-    flags.
-
-Optional properties:
-- reg : Base address and length of the GIC registers.  If not present,
-  the base address reported by the hardware GCR_GIC_BASE will be used.
-- mti,reserved-cpu-vectors : Specifies the list of CPU interrupt vectors
-  to which the GIC may not route interrupts.  Valid values are 2 - 7.
-  This property is ignored if the CPU is started in EIC mode.
-- mti,reserved-ipi-vectors : Specifies the range of GIC interrupts that are
-  reserved for IPIs.
-  It accepts 2 values, the 1st is the starting interrupt and the 2nd is the size
-  of the reserved range.
-  If not specified, the driver will allocate the last 2 * number of VPEs in the
-  system.
-
-Required properties for timer sub-node:
-- compatible : Should be "mti,gic-timer".
-- interrupts : Interrupt for the GIC local timer.
-
-Optional properties for timer sub-node:
-- clocks : GIC timer operating clock.
-- clock-frequency : Clock frequency at which the GIC timers operate.
-
-Note that one of clocks or clock-frequency must be specified.
-
-Example:
-
-	gic: interrupt-controller@1bdc0000 {
-		compatible = "mti,gic";
-		reg = <0x1bdc0000 0x20000>;
-
-		interrupt-controller;
-		#interrupt-cells = <3>;
-
-		mti,reserved-cpu-vectors = <7>;
-		mti,reserved-ipi-vectors = <40 8>;
-
-		timer {
-			compatible = "mti,gic-timer";
-			interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
-			clock-frequency = <50000000>;
-		};
-	};
-
-	uart@18101400 {
-		...
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
-		...
-	};
diff --git a/Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml b/Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml
new file mode 100644
index 000000000000..9f0eb3addac4
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml
@@ -0,0 +1,148 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MIPS Global Interrupt Controller
+
+maintainers:
+  - Paul Burton <paulburton@kernel.org>
+  - Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+
+description: |
+  The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
+  It also supports local (per-processor) interrupts and software-generated
+  interrupts which can be used as IPIs. The GIC also includes a free-running
+  global timer, per-CPU count/compare timers, and a watchdog.
+
+properties:
+  compatible:
+    const: mti,gic
+
+  "#interrupt-cells":
+    const: 3
+    description: |
+      The 1st cell is the type of interrupt: local or shared defined in the
+      file 'dt-bindings/interrupt-controller/mips-gic.h'. The 2nd cell is the
+      GIC interrupt number. The 3d cell encodes the interrupt flags setting up
+      the IRQ trigger modes, which are defined in the file
+      'dt-bindings/interrupt-controller/irq.h'.
+
+  reg:
+    description: |
+      Base address and length of the GIC registers space. If not present,
+      the base address reported by the hardware GCR_GIC_BASE will be used.
+    maxItems: 1
+
+  interrupt-controller: true
+
+  mti,reserved-cpu-vectors:
+    description: |
+      Specifies the list of CPU interrupt vectors to which the GIC may not
+      route interrupts. This property is ignored if the CPU is started in EIC
+      mode.
+    allOf:
+      - $ref: /schemas/types.yaml#definitions/uint32-array
+      - minItems: 1
+        maxItems: 6
+        uniqueItems: true
+        items:
+          minimum: 2
+          maximum: 7
+
+  mti,reserved-ipi-vectors:
+    description: |
+      Specifies the range of GIC interrupts that are reserved for IPIs.
+      It accepts two values: the 1st is the starting interrupt and the 2nd is
+      the size of the reserved range. If not specified, the driver will
+      allocate the last (2 * number of VPEs in the system).
+    allOf:
+      - $ref: /schemas/types.yaml#definitions/uint32-array
+      - items:
+          - minimum: 0
+            maximum: 254
+          - minimum: 2
+            maximum: 254
+
+  timer:
+    type: object
+    description: |
+      MIPS GIC includes a free-running global timer, per-CPU count/compare
+      timers, and a watchdog. Currently only the GIC Timer is supported.
+    properties:
+      compatible:
+        const: mti,gic-timer
+
+      interrupts:
+        description: |
+          Interrupt for the GIC local timer, so normally it's suppose to be of
+          <GIC_LOCAL X IRQ_TYPE_NONE> format.
+        maxItems: 1
+
+      clocks:
+        maxItems: 1
+
+      clock-frequency: true
+
+    required:
+      - compatible
+      - interrupts
+
+    oneOf:
+      - required:
+          - clocks
+      - required:
+          - clock-frequency
+
+    additionalProperties: false
+
+unevaluatedProperties: false
+
+required:
+  - compatible
+  - "#interrupt-cells"
+  - interrupt-controller
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/mips-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    interrupt-controller@1bdc0000 {
+      compatible = "mti,gic";
+      reg = <0x1bdc0000 0x20000>;
+      interrupt-controller;
+      #interrupt-cells = <3>;
+      mti,reserved-cpu-vectors = <7>;
+      mti,reserved-ipi-vectors = <40 8>;
+
+      timer {
+        compatible = "mti,gic-timer";
+        interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
+        clock-frequency = <50000000>;
+      };
+    };
+  - |
+    #include <dt-bindings/interrupt-controller/mips-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    interrupt-controller@1bdc0000 {
+      compatible = "mti,gic";
+      reg = <0x1bdc0000 0x20000>;
+      interrupt-controller;
+      #interrupt-cells = <3>;
+
+      timer {
+        compatible = "mti,gic-timer";
+        interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
+        clocks = <&cpu_pll>;
+      };
+    };
+  - |
+    interrupt-controller {
+      compatible = "mti,gic";
+      interrupt-controller;
+      #interrupt-cells = <3>;
+    };
+...
-- 
2.25.1

Re: [PATCH v3 3/7] dt-bindings: interrupt-controller: Convert mti,gic to DT schema

[Rob Herring]

On Thu, 7 May 2020 00:41:03 +0300, Serge Semin wrote:
> Modern device tree bindings are supposed to be created as YAML-files
> in accordance with DT schema. This commit replaces MIPS GIC legacy bare
> text binding with YAML file. As before the binding file states that the
> corresponding dts node is supposed to be compatible with MIPS Global
> Interrupt Controller indicated by the "mti,gic" compatible string and
> to provide a mandatory interrupt-controller and '#interrupt-cells'
> properties. There might be optional registers memory range,
> "mti,reserved-cpu-vectors" and "mti,reserved-ipi-vectors" properties
> specified.
> 
> MIPS GIC also includes a free-running global timer, per-CPU count/compare
> timers, and a watchdog. Since currently the GIC Timer is only supported the
> DT schema expects an IRQ and clock-phandler charged timer sub-node with
> "mti,mips-gic-timer" compatible string.
> 
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: Paul Burton <paulburton@kernel.org>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: Alessandro Zummo <a.zummo@towertech.it>
> Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
> Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: linux-mips@vger.kernel.org
> Cc: linux-rtc@vger.kernel.org
> 
> ---
> 
> I don't really know who is the corresponding driver maintainer, so I
> added Paul to the maintainers property since he used to be looking for the
> MIPS arch and Thomas looking after it now. Any idea what email should be
> specified there instead?
> 
> Changelog v3:
> - Since timer sub-node has no unit-address, the node shouldn't be named
>   with one. So alter the MIPS GIC bindings to have a pure "timer"
>   sub-node.
> - Discard allOf: [ $ref: /schemas/interrupt-controller.yaml# ].
> - Since it's a conversion patch use GPL-2.0-only SPDX header.
> ---
>  .../interrupt-controller/mips-gic.txt         |  67 --------
>  .../interrupt-controller/mti,gic.yaml         | 148 ++++++++++++++++++
>  2 files changed, 148 insertions(+), 67 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml
> 

Reviewed-by: Rob Herring <robh@kernel.org>

Re: [PATCH v3 3/7] dt-bindings: interrupt-controller: Convert mti,gic to DT schema

[Serge Semin]

Thomas, Jason, Marc
Could you take a look at this patch and merge it in if you are ok with its
content. We've got Rob's Reviewed-by tag here, so it's only waiting for your
acceptance.

-Sergey

On Thu, May 14, 2020 at 02:06:32PM -0500, Rob Herring wrote:
> On Thu, 7 May 2020 00:41:03 +0300, Serge Semin wrote:
> > Modern device tree bindings are supposed to be created as YAML-files
> > in accordance with DT schema. This commit replaces MIPS GIC legacy bare
> > text binding with YAML file. As before the binding file states that the
> > corresponding dts node is supposed to be compatible with MIPS Global
> > Interrupt Controller indicated by the "mti,gic" compatible string and
> > to provide a mandatory interrupt-controller and '#interrupt-cells'
> > properties. There might be optional registers memory range,
> > "mti,reserved-cpu-vectors" and "mti,reserved-ipi-vectors" properties
> > specified.
> > 
> > MIPS GIC also includes a free-running global timer, per-CPU count/compare
> > timers, and a watchdog. Since currently the GIC Timer is only supported the
> > DT schema expects an IRQ and clock-phandler charged timer sub-node with
> > "mti,mips-gic-timer" compatible string.
> > 
> > Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> > Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> > Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> > Cc: Paul Burton <paulburton@kernel.org>
> > Cc: Ralf Baechle <ralf@linux-mips.org>
> > Cc: Alessandro Zummo <a.zummo@towertech.it>
> > Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
> > Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
> > Cc: Arnd Bergmann <arnd@arndb.de>
> > Cc: linux-mips@vger.kernel.org
> > Cc: linux-rtc@vger.kernel.org
> > 
> > ---
> > 
> > I don't really know who is the corresponding driver maintainer, so I
> > added Paul to the maintainers property since he used to be looking for the
> > MIPS arch and Thomas looking after it now. Any idea what email should be
> > specified there instead?
> > 
> > Changelog v3:
> > - Since timer sub-node has no unit-address, the node shouldn't be named
> >   with one. So alter the MIPS GIC bindings to have a pure "timer"
> >   sub-node.
> > - Discard allOf: [ $ref: /schemas/interrupt-controller.yaml# ].
> > - Since it's a conversion patch use GPL-2.0-only SPDX header.
> > ---
> >  .../interrupt-controller/mips-gic.txt         |  67 --------
> >  .../interrupt-controller/mti,gic.yaml         | 148 ++++++++++++++++++
> >  2 files changed, 148 insertions(+), 67 deletions(-)
> >  delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
> >  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml
> > 
> 
> Reviewed-by: Rob Herring <robh@kernel.org>

[PATCH v3 4/7] clocksource: dw_apb_timer: Set clockevent any-possible-CPU mask

[Serge Semin]

Currently the DW APB Timer driver binds all clockevent timers to
CPU #0. This isn't good for multiple reasons. First of all seeing
the device is placed on APB bus (which makes it accessible from any
CPU core), accessible over MMIO and having the DYNIRQ flag set we
can be sure that manually binding the timer to any CPU just isn't
correct. By doing so we just set an extra limitation on device usage.
This also doesn't reflect the device actual capability, since by
setting the IRQ affinity we can make it virtually local to any CPU.
Secondly imagine if you had a real CPU-local timer with the same
rating and the same CPU-affinity. In this case if DW APB timer was
registered first, then due to the clockevent framework tick-timer
selection procedure we'll end up with the real CPU-local timer being
left unselected for clock-events tracking. But on most of the platforms
(MIPS/ARM/etc) such timers are normally embedded into the CPU core and
are accessible with much better performance then devices placed on APB.
For instance in MIPS architectures there is r4k-timer, which is
CPU-local, assigned with the same rating, and normally its
clockevent device is registered after the platform-specific one.

So in order to fix all of these issues lets set the DW APB clockevent
timer cpumask to be 'cpu_possible_mask'. By doing so the clockevent
framework would prefer to select the real CPU-local timer instead
of DW APB one. Otherwise if there is no other than DW APB device for
clockevents tracking then it will be selected.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Alessandro Zummo <a.zummo@towertech.it>
Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: linux-rtc@vger.kernel.org
Cc: devicetree@vger.kernel.org
---
 drivers/clocksource/dw_apb_timer.c    | 18 +++++++-----------
 drivers/clocksource/dw_apb_timer_of.c |  3 +--
 include/linux/dw_apb_timer.h          |  2 +-
 3 files changed, 9 insertions(+), 14 deletions(-)

diff --git a/drivers/clocksource/dw_apb_timer.c b/drivers/clocksource/dw_apb_timer.c
index b207a77b0831..8ebb43916423 100644
--- a/drivers/clocksource/dw_apb_timer.c
+++ b/drivers/clocksource/dw_apb_timer.c
@@ -106,6 +106,7 @@ static irqreturn_t dw_apb_clockevent_irq(int irq, void *data)
 		dw_ced->eoi(&dw_ced->timer);
 
 	evt->event_handler(evt);
+
 	return IRQ_HANDLED;
 }
 
@@ -123,8 +124,7 @@ static int apbt_shutdown(struct clock_event_device *evt)
 	struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
 	u32 ctrl;
 
-	pr_debug("%s CPU %d state=shutdown\n", __func__,
-		 cpumask_first(evt->cpumask));
+	pr_debug("%s state=shutdown\n", __func__);
 
 	ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
 	ctrl &= ~APBTMR_CONTROL_ENABLE;
@@ -137,8 +137,7 @@ static int apbt_set_oneshot(struct clock_event_device *evt)
 	struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
 	u32 ctrl;
 
-	pr_debug("%s CPU %d state=oneshot\n", __func__,
-		 cpumask_first(evt->cpumask));
+	pr_debug("%s state=oneshot\n", __func__);
 
 	ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
 	/*
@@ -170,8 +169,7 @@ static int apbt_set_periodic(struct clock_event_device *evt)
 	unsigned long period = DIV_ROUND_UP(dw_ced->timer.freq, HZ);
 	u32 ctrl;
 
-	pr_debug("%s CPU %d state=periodic\n", __func__,
-		 cpumask_first(evt->cpumask));
+	pr_debug("%s state=periodic\n", __func__);
 
 	ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
 	ctrl |= APBTMR_CONTROL_MODE_PERIODIC;
@@ -194,8 +192,7 @@ static int apbt_resume(struct clock_event_device *evt)
 {
 	struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
 
-	pr_debug("%s CPU %d state=resume\n", __func__,
-		 cpumask_first(evt->cpumask));
+	pr_debug("%s state=resume\n", __func__);
 
 	apbt_enable_int(&dw_ced->timer);
 	return 0;
@@ -222,7 +219,6 @@ static int apbt_next_event(unsigned long delta,
 /**
  * dw_apb_clockevent_init() - use an APB timer as a clock_event_device
  *
- * @cpu:	The CPU the events will be targeted at.
  * @name:	The name used for the timer and the IRQ for it.
  * @rating:	The rating to give the timer.
  * @base:	I/O base for the timer registers.
@@ -237,7 +233,7 @@ static int apbt_next_event(unsigned long delta,
  * releasing the IRQ.
  */
 struct dw_apb_clock_event_device *
-dw_apb_clockevent_init(int cpu, const char *name, unsigned rating,
+dw_apb_clockevent_init(const char *name, unsigned int rating,
 		       void __iomem *base, int irq, unsigned long freq)
 {
 	struct dw_apb_clock_event_device *dw_ced =
@@ -257,7 +253,7 @@ dw_apb_clockevent_init(int cpu, const char *name, unsigned rating,
 	dw_ced->ced.max_delta_ticks = 0x7fffffff;
 	dw_ced->ced.min_delta_ns = clockevent_delta2ns(5000, &dw_ced->ced);
 	dw_ced->ced.min_delta_ticks = 5000;
-	dw_ced->ced.cpumask = cpumask_of(cpu);
+	dw_ced->ced.cpumask = cpu_possible_mask;
 	dw_ced->ced.features = CLOCK_EVT_FEAT_PERIODIC |
 				CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_DYNIRQ;
 	dw_ced->ced.set_state_shutdown = apbt_shutdown;
diff --git a/drivers/clocksource/dw_apb_timer_of.c b/drivers/clocksource/dw_apb_timer_of.c
index 8c28b127759f..0a2505b323d7 100644
--- a/drivers/clocksource/dw_apb_timer_of.c
+++ b/drivers/clocksource/dw_apb_timer_of.c
@@ -73,8 +73,7 @@ static void __init add_clockevent(struct device_node *event_timer)
 
 	timer_get_base_and_rate(event_timer, &iobase, &rate);
 
-	ced = dw_apb_clockevent_init(0, event_timer->name, 300, iobase, irq,
-				     rate);
+	ced = dw_apb_clockevent_init(event_timer->name, 300, iobase, irq, rate);
 	if (!ced)
 		panic("Unable to initialise clockevent device");
 
diff --git a/include/linux/dw_apb_timer.h b/include/linux/dw_apb_timer.h
index 82ebf9223948..689022bc8d17 100644
--- a/include/linux/dw_apb_timer.h
+++ b/include/linux/dw_apb_timer.h
@@ -39,7 +39,7 @@ void dw_apb_clockevent_resume(struct dw_apb_clock_event_device *dw_ced);
 void dw_apb_clockevent_stop(struct dw_apb_clock_event_device *dw_ced);
 
 struct dw_apb_clock_event_device *
-dw_apb_clockevent_init(int cpu, const char *name, unsigned rating,
+dw_apb_clockevent_init(const char *name, unsigned int rating,
 		       void __iomem *base, int irq, unsigned long freq);
 struct dw_apb_clocksource *
 dw_apb_clocksource_init(unsigned rating, const char *name, void __iomem *base,
-- 
2.25.1

[PATCH v3 5/7] clocksource: dw_apb_timer_of: Fix missing clockevent timers

[Serge Semin]

Commit 100214889973 ("clocksource: dw_apb_timer_of: use
clocksource_of_init") replaced a publicly available driver
initialization method with one called by the timer_probe() method
available after CLKSRC_OF. In current implementation it traverses
all the timers available in the system and calls their initialization
methods if corresponding devices were either in dtb or in acpi. But
if before the commit any number of available timers would be installed
as clockevent and clocksource devices, after that there would be at most
two. The rest are just ignored since default case branch doesn't do
anything. I don't see a reason of such behaviour, neither the commit
message explains it. Moreover this might be wrong if on some platforms
these timers might be used for different purpose, as virtually CPU-local
clockevent timers and as an independent broadcast timer. So in order
to keep the compatibility with the platforms where the order of the
timers detection has some meaning, lets add the secondly discovered
timer to be of clocksource/sched_clock type, while the very first and
the others would provide the clockevents service.

Fixes: 100214889973 ("clocksource: dw_apb_timer_of: use clocksource_of_init")
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Alessandro Zummo <a.zummo@towertech.it>
Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: linux-rtc@vger.kernel.org
Cc: devicetree@vger.kernel.org
---
 drivers/clocksource/dw_apb_timer_of.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/clocksource/dw_apb_timer_of.c b/drivers/clocksource/dw_apb_timer_of.c
index 0a2505b323d7..0b61b90a525e 100644
--- a/drivers/clocksource/dw_apb_timer_of.c
+++ b/drivers/clocksource/dw_apb_timer_of.c
@@ -146,10 +146,6 @@ static int num_called;
 static int __init dw_apb_timer_init(struct device_node *timer)
 {
 	switch (num_called) {
-	case 0:
-		pr_debug("%s: found clockevent timer\n", __func__);
-		add_clockevent(timer);
-		break;
 	case 1:
 		pr_debug("%s: found clocksource timer\n", __func__);
 		add_clocksource(timer);
@@ -160,6 +156,8 @@ static int __init dw_apb_timer_init(struct device_node *timer)
 #endif
 		break;
 	default:
+		pr_debug("%s: found clockevent timer\n", __func__);
+		add_clockevent(timer);
 		break;
 	}
 
-- 
2.25.1

[PATCH v3 6/7] clocksource: mips-gic-timer: Register as sched_clock

[Serge Semin]

From: Paul Burton <paulburton@kernel.org>

From: Paul Burton <paulburton@kernel.org>

The MIPS GIC timer is well suited for use as sched_clock, so register it
as such.

Whilst the existing gic_read_count() function matches the prototype
needed by sched_clock_register() already, we split it into 2 functions
in order to remove the need to evaluate the mips_cm_is64 condition
within each call since sched_clock should be as fast as possible.

Signed-off-by: Paul Burton <paulburton@kernel.org>
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Alessandro Zummo <a.zummo@towertech.it>
Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: linux-rtc@vger.kernel.org
Cc: devicetree@vger.kernel.org
---
 drivers/clocksource/mips-gic-timer.c | 23 +++++++++++++++++++----
 1 file changed, 19 insertions(+), 4 deletions(-)

diff --git a/drivers/clocksource/mips-gic-timer.c b/drivers/clocksource/mips-gic-timer.c
index 8b5f8ae723cb..802b93fe3ae7 100644
--- a/drivers/clocksource/mips-gic-timer.c
+++ b/drivers/clocksource/mips-gic-timer.c
@@ -16,6 +16,7 @@
 #include <linux/notifier.h>
 #include <linux/of_irq.h>
 #include <linux/percpu.h>
+#include <linux/sched_clock.h>
 #include <linux/smp.h>
 #include <linux/time.h>
 #include <asm/mips-cps.h>
@@ -24,13 +25,10 @@ static DEFINE_PER_CPU(struct clock_event_device, gic_clockevent_device);
 static int gic_timer_irq;
 static unsigned int gic_frequency;
 
-static u64 notrace gic_read_count(void)
+static u64 notrace gic_read_count_2x32(void)
 {
 	unsigned int hi, hi2, lo;
 
-	if (mips_cm_is64)
-		return read_gic_counter();
-
 	do {
 		hi = read_gic_counter_32h();
 		lo = read_gic_counter_32l();
@@ -40,6 +38,19 @@ static u64 notrace gic_read_count(void)
 	return (((u64) hi) << 32) + lo;
 }
 
+static u64 notrace gic_read_count_64(void)
+{
+	return read_gic_counter();
+}
+
+static u64 notrace gic_read_count(void)
+{
+	if (mips_cm_is64)
+		return gic_read_count_64();
+
+	return gic_read_count_2x32();
+}
+
 static int gic_next_event(unsigned long delta, struct clock_event_device *evt)
 {
 	int cpu = cpumask_first(evt->cpumask);
@@ -228,6 +239,10 @@ static int __init gic_clocksource_of_init(struct device_node *node)
 	/* And finally start the counter */
 	clear_gic_config(GIC_CONFIG_COUNTSTOP);
 
+	sched_clock_register(mips_cm_is64 ?
+			     gic_read_count_64 : gic_read_count_2x32,
+			     64, gic_frequency);
+
 	return 0;
 }
 TIMER_OF_DECLARE(mips_gic_timer, "mti,gic-timer",
-- 
2.25.1

[PATCH v3 7/7] clocksource: mips-gic-timer: Set limitations on clocksource/sched-clocks usage

[Serge Semin]

Currently neither clocksource nor scheduler clock kernel framework
support the clocks with variable frequency. Needless to say how many
problems may cause the sudden base clocks frequency change. In a
simplest case the system time will either slow down or speed up.
Since on CM2.5 and earlier MIPS GIC timer is synchronously clocked
with CPU we must set some limitations on using it for these frameworks
if CPU frequency may change. First of all it's not safe to have the
MIPS GIC used for scheduler timings. So we shouldn't proceed with
the clocks registration in the sched-subsystem. Secondly we must
significantly decrease the MIPS GIC clocksource rating. This will let
the system to use it only as a last resort.

Note CM3.x-based systems may also experience the problems with MIPS GIC
if the CPU-frequency change is activated for the whole CPU cluster
instead of using the individual CPC core clocks divider.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Alessandro Zummo <a.zummo@towertech.it>
Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: linux-rtc@vger.kernel.org
Cc: devicetree@vger.kernel.org
---
 drivers/clocksource/mips-gic-timer.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/clocksource/mips-gic-timer.c b/drivers/clocksource/mips-gic-timer.c
index 802b93fe3ae7..095d65b48920 100644
--- a/drivers/clocksource/mips-gic-timer.c
+++ b/drivers/clocksource/mips-gic-timer.c
@@ -185,7 +185,10 @@ static int __init __gic_clocksource_init(void)
 	gic_clocksource.mask = CLOCKSOURCE_MASK(count_width);
 
 	/* Calculate a somewhat reasonable rating value. */
-	gic_clocksource.rating = 200 + gic_frequency / 10000000;
+	if (mips_cm_revision() >= CM_REV_CM3 || !IS_ENABLED(CONFIG_CPU_FREQ))
+		gic_clocksource.rating = 200 + gic_frequency / 10000000;
+	else
+		gic_clocksource.rating = 99;
 
 	ret = clocksource_register_hz(&gic_clocksource, gic_frequency);
 	if (ret < 0)
@@ -239,9 +242,11 @@ static int __init gic_clocksource_of_init(struct device_node *node)
 	/* And finally start the counter */
 	clear_gic_config(GIC_CONFIG_COUNTSTOP);
 
-	sched_clock_register(mips_cm_is64 ?
-			     gic_read_count_64 : gic_read_count_2x32,
-			     64, gic_frequency);
+	if (mips_cm_revision() >= CM_REV_CM3 || !IS_ENABLED(CONFIG_CPU_FREQ)) {
+		sched_clock_register(mips_cm_is64 ?
+				     gic_read_count_64 : gic_read_count_2x32,
+				     64, gic_frequency);
+	}
 
 	return 0;
 }
-- 
2.25.1

Re: [PATCH v3 7/7] clocksource: mips-gic-timer: Set limitations on clocksource/sched-clocks usage

[Daniel Lezcano]

On Thu, May 07, 2020 at 12:41:07AM +0300, Serge Semin wrote:
> Currently neither clocksource nor scheduler clock kernel framework
> support the clocks with variable frequency. Needless to say how many
> problems may cause the sudden base clocks frequency change. In a
> simplest case the system time will either slow down or speed up.
> Since on CM2.5 and earlier MIPS GIC timer is synchronously clocked
> with CPU we must set some limitations on using it for these frameworks
> if CPU frequency may change. First of all it's not safe to have the
> MIPS GIC used for scheduler timings. So we shouldn't proceed with
> the clocks registration in the sched-subsystem. Secondly we must
> significantly decrease the MIPS GIC clocksource rating. This will let
> the system to use it only as a last resort.
>
> Note CM3.x-based systems may also experience the problems with MIPS GIC
> if the CPU-frequency change is activated for the whole CPU cluster
> instead of using the individual CPC core clocks divider.

May be there is no alternative but the code looks a bit hacksih. Isn't possible
to do something with the sched_mark_unstable?

Or just not use the timer at all ?

Re: [PATCH v3 7/7] clocksource: mips-gic-timer: Set limitations on clocksource/sched-clocks usage

[Serge Semin]

Hello Daniel,

Thanks for your comment. My response is below.

On Fri, May 15, 2020 at 07:10:04PM +0200, Daniel Lezcano wrote:
> On Thu, May 07, 2020 at 12:41:07AM +0300, Serge Semin wrote:
> > Currently neither clocksource nor scheduler clock kernel framework
> > support the clocks with variable frequency. Needless to say how many
> > problems may cause the sudden base clocks frequency change. In a
> > simplest case the system time will either slow down or speed up.
> > Since on CM2.5 and earlier MIPS GIC timer is synchronously clocked
> > with CPU we must set some limitations on using it for these frameworks
> > if CPU frequency may change. First of all it's not safe to have the
> > MIPS GIC used for scheduler timings. So we shouldn't proceed with
> > the clocks registration in the sched-subsystem. Secondly we must
> > significantly decrease the MIPS GIC clocksource rating. This will let
> > the system to use it only as a last resort.
> >
> > Note CM3.x-based systems may also experience the problems with MIPS GIC
> > if the CPU-frequency change is activated for the whole CPU cluster
> > instead of using the individual CPC core clocks divider.
> 
> May be there is no alternative but the code looks a bit hacksih. Isn't possible
> to do something with the sched_mark_unstable?
> 
> Or just not use the timer at all ?

Not using the timer might be better, but not that good alternative either
especially in our case due to very slow external timer. Me and Thomas
Bogendoerfer discussed the similar commit I've provided to the csrc-r4k driver
available on MIPS:
https://lkml.org/lkml/2020/5/11/576

To cut it short, you are right. The solution with using clocksource_mark_unstable()
is better alternative spied up in x86 tsc implementation. I'll use a similar
approach here and submit the updated patch in v3.

Could you please proceed with the rest of the series review? I'd like to send
the next version with as many comments taken into account as possible. The
patchset has been submitted a while ago, but except Rob noone have had any
comments.(

-Sergey

Re: [PATCH v3 7/7] clocksource: mips-gic-timer: Set limitations on clocksource/sched-clocks usage

[Daniel Lezcano]

On 16/05/2020 14:16, Serge Semin wrote:
> Hello Daniel,
> 
> Thanks for your comment. My response is below.
> 
> On Fri, May 15, 2020 at 07:10:04PM +0200, Daniel Lezcano wrote:
>> On Thu, May 07, 2020 at 12:41:07AM +0300, Serge Semin wrote:
>>> Currently neither clocksource nor scheduler clock kernel framework
>>> support the clocks with variable frequency. Needless to say how many
>>> problems may cause the sudden base clocks frequency change. In a
>>> simplest case the system time will either slow down or speed up.
>>> Since on CM2.5 and earlier MIPS GIC timer is synchronously clocked
>>> with CPU we must set some limitations on using it for these frameworks
>>> if CPU frequency may change. First of all it's not safe to have the
>>> MIPS GIC used for scheduler timings. So we shouldn't proceed with
>>> the clocks registration in the sched-subsystem. Secondly we must
>>> significantly decrease the MIPS GIC clocksource rating. This will let
>>> the system to use it only as a last resort.
>>>
>>> Note CM3.x-based systems may also experience the problems with MIPS GIC
>>> if the CPU-frequency change is activated for the whole CPU cluster
>>> instead of using the individual CPC core clocks divider.
>>
>> May be there is no alternative but the code looks a bit hacksih. Isn't possible
>> to do something with the sched_mark_unstable?
>>
>> Or just not use the timer at all ?
> 
> Not using the timer might be better, but not that good alternative either
> especially in our case due to very slow external timer. Me and Thomas
> Bogendoerfer discussed the similar commit I've provided to the csrc-r4k driver
> available on MIPS:
> https://lkml.org/lkml/2020/5/11/576
> 
> To cut it short, you are right. The solution with using clocksource_mark_unstable()
> is better alternative spied up in x86 tsc implementation. I'll use a similar
> approach here and submit the updated patch in v3.
> 
> Could you please proceed with the rest of the series review? I'd like to send
> the next version with as many comments taken into account as possible. The
> patchset has been submitted a while ago, but except Rob noone have had any
> comments.(

For me other patches are ok.

I can apply patches 1, 2, 4, 5, 6

Will remain patches 3 et 7


-- 
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
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<http://www.linaro.org/linaro-blog/> Blog

Re: [PATCH v3 7/7] clocksource: mips-gic-timer: Set limitations on clocksource/sched-clocks usage

[Serge Semin]

Daniel,

On Mon, May 18, 2020 at 03:59:16PM +0200, Daniel Lezcano wrote:
> On 16/05/2020 14:16, Serge Semin wrote:
> > Hello Daniel,
> > 
> > Thanks for your comment. My response is below.
> > 
> > On Fri, May 15, 2020 at 07:10:04PM +0200, Daniel Lezcano wrote:
> >> On Thu, May 07, 2020 at 12:41:07AM +0300, Serge Semin wrote:
> >>> Currently neither clocksource nor scheduler clock kernel framework
> >>> support the clocks with variable frequency. Needless to say how many
> >>> problems may cause the sudden base clocks frequency change. In a
> >>> simplest case the system time will either slow down or speed up.
> >>> Since on CM2.5 and earlier MIPS GIC timer is synchronously clocked
> >>> with CPU we must set some limitations on using it for these frameworks
> >>> if CPU frequency may change. First of all it's not safe to have the
> >>> MIPS GIC used for scheduler timings. So we shouldn't proceed with
> >>> the clocks registration in the sched-subsystem. Secondly we must
> >>> significantly decrease the MIPS GIC clocksource rating. This will let
> >>> the system to use it only as a last resort.
> >>>
> >>> Note CM3.x-based systems may also experience the problems with MIPS GIC
> >>> if the CPU-frequency change is activated for the whole CPU cluster
> >>> instead of using the individual CPC core clocks divider.
> >>
> >> May be there is no alternative but the code looks a bit hacksih. Isn't possible
> >> to do something with the sched_mark_unstable?
> >>
> >> Or just not use the timer at all ?
> > 
> > Not using the timer might be better, but not that good alternative either
> > especially in our case due to very slow external timer. Me and Thomas
> > Bogendoerfer discussed the similar commit I've provided to the csrc-r4k driver
> > available on MIPS:
> > https://lkml.org/lkml/2020/5/11/576
> > 
> > To cut it short, you are right. The solution with using clocksource_mark_unstable()
> > is better alternative spied up in x86 tsc implementation. I'll use a similar
> > approach here and submit the updated patch in v3.
> > 
> > Could you please proceed with the rest of the series review? I'd like to send
> > the next version with as many comments taken into account as possible. The
> > patchset has been submitted a while ago, but except Rob noone have had any
> > comments.(
> 
> For me other patches are ok.
> 
> I can apply patches 1, 2, 4, 5, 6
> 
> Will remain patches 3 et 7

That's be great! Thanks. Is patch 3 supposed to be merged in by Rob or by you?
I don't see one being in the Rob's repo. He might be waiting for you
acknowledgment or something.

I'll send the updated patch 3 shortly today.

-Sergey

> 
> 
> -- 
> <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
> 
> Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
> <http://twitter.com/#!/linaroorg> Twitter |
> <http://www.linaro.org/linaro-blog/> Blog

Re: [PATCH v3 7/7] clocksource: mips-gic-timer: Set limitations on clocksource/sched-clocks usage

[Serge Semin]

On Mon, May 18, 2020 at 05:40:46PM +0300, Serge Semin wrote:
> Daniel,
> 
> On Mon, May 18, 2020 at 03:59:16PM +0200, Daniel Lezcano wrote:
> > On 16/05/2020 14:16, Serge Semin wrote:
> > > Hello Daniel,
> > > 
> > > Thanks for your comment. My response is below.
> > > 
> > > On Fri, May 15, 2020 at 07:10:04PM +0200, Daniel Lezcano wrote:
> > >> On Thu, May 07, 2020 at 12:41:07AM +0300, Serge Semin wrote:
> > >>> Currently neither clocksource nor scheduler clock kernel framework
> > >>> support the clocks with variable frequency. Needless to say how many
> > >>> problems may cause the sudden base clocks frequency change. In a
> > >>> simplest case the system time will either slow down or speed up.
> > >>> Since on CM2.5 and earlier MIPS GIC timer is synchronously clocked
> > >>> with CPU we must set some limitations on using it for these frameworks
> > >>> if CPU frequency may change. First of all it's not safe to have the
> > >>> MIPS GIC used for scheduler timings. So we shouldn't proceed with
> > >>> the clocks registration in the sched-subsystem. Secondly we must
> > >>> significantly decrease the MIPS GIC clocksource rating. This will let
> > >>> the system to use it only as a last resort.
> > >>>
> > >>> Note CM3.x-based systems may also experience the problems with MIPS GIC
> > >>> if the CPU-frequency change is activated for the whole CPU cluster
> > >>> instead of using the individual CPC core clocks divider.
> > >>
> > >> May be there is no alternative but the code looks a bit hacksih. Isn't possible
> > >> to do something with the sched_mark_unstable?
> > >>
> > >> Or just not use the timer at all ?
> > > 
> > > Not using the timer might be better, but not that good alternative either
> > > especially in our case due to very slow external timer. Me and Thomas
> > > Bogendoerfer discussed the similar commit I've provided to the csrc-r4k driver
> > > available on MIPS:
> > > https://lkml.org/lkml/2020/5/11/576
> > > 
> > > To cut it short, you are right. The solution with using clocksource_mark_unstable()
> > > is better alternative spied up in x86 tsc implementation. I'll use a similar
> > > approach here and submit the updated patch in v3.
> > > 
> > > Could you please proceed with the rest of the series review? I'd like to send
> > > the next version with as many comments taken into account as possible. The
> > > patchset has been submitted a while ago, but except Rob noone have had any
> > > comments.(
> > 
> > For me other patches are ok.
> > 
> > I can apply patches 1, 2, 4, 5, 6
> > 
> > Will remain patches 3 et 7
> 
> That's be great! Thanks. Is patch 3 supposed to be merged in by Rob or by you?
> I don't see one being in the Rob's repo. He might be waiting for you
> acknowledgment or something.

Ah, it's about the MIPS GIC IRQchip bindings conversion. No questions tabout
patch 3then. I'll ask Thomas about that patch status.

-Sergey 

> 
> I'll send the updated patch 3 shortly today.
> 
> -Sergey
> 
> > 
> > 
> > -- 
> > <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
> > 
> > Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
> > <http://twitter.com/#!/linaroorg> Twitter |
> > <http://www.linaro.org/linaro-blog/> Blog

[PATCH RESEND v2 0/6] mips: Add DT bindings for MIPS CDMM and MIPS GIC

[Serge Semin]

Folks, the code and DT-related patches here have been mostly reviewed.
Please consider merge the series in or at least give me a feedback to
update the series, since merge window is getting opened tomorrow and I
would really appreciate to see the leftover being merged in.

Regarding this patchset origin. Recently I've submitted a series of
patchset's which provided multiple fixes for the MIPS arch subsystem and
the MIPS GIC and DW APB Timer drivers, which were required for the
Baikal-T1 SoC correctly working with those drivers. Mostly those patchsets
have been already merged into the corresponding subsystems, but several
patches have been left floating since noone really responded for review
except Rob provided his approval regarding DT bindings. Thus in this
patchset I've collected all the leftovers so not to loose them in a pale
of the maintainers email logs.

The patchset includes the following updates: MIPS CPC and GIC DT bindings
legacy text-based file are converted to the DT schema (Rob has already
reviewed them), add MIPS CDMM DT node support to place the CDMM block at
the platform-specific MMIO range, make sure MIPS CDMM is available for
MIPS_R5 CPUs.

Seeing the series concerns the MIPS-related drivers it's better to merge
it in through the MIPS repository:
https://git.kernel.org/pub/scm/linux/kernel/git/mips/linux.git/

This patchset is rebased and tested on the mainline Linux kernel 5.7-rc4:
base-commit: 0e698dfa2822 ("Linux 5.7-rc4")
tag: v5.7-rc4

Suggestion.
Since Paul isn't looking after the MIPS arch code anymore, Ralf hasn't
been seen maintaining MIPS for a long time, Thomas is only responsible
for the next part of it:
	F:      Documentation/devicetree/bindings/mips/
	F:      Documentation/mips/
	F:      arch/mips/
	F:      drivers/platform/mips/
the MIPS-specific drivers like:
	F:	drivers/bus/mips_cdmm.c
	F:	drivers/irqchip/irq-mips-cpu.c
	F:	drivers/irqchip/irq-mips-gic.c
	F:	drivers/clocksource/mips-gic-timer.c
	F:	drivers/cpuidle/cpuidle-cps.c
seem to be left for the subsystems maintainers to support. So if you don't
mind or unless there is a better alternative, I can help with looking
after them to ease the maintainers review burden and since I'll be working
on our MIPS-based SoC drivers integrating into the mainline kernel repo
anyway. If you don't like this idea, please just decline the last
patch in the series.

Previous patchsets:
mips: Prepare MIPS-arch code for Baikal-T1 SoC support:
Link: https://lore.kernel.org/linux-mips/20200306124807.3596F80307C2@mail.baikalelectronics.ru
Link: https://lore.kernel.org/linux-mips/20200506174238.15385-1-Sergey.Semin@baikalelectronics.ru
Link: https://lore.kernel.org/linux-mips/20200521140725.29571-1-Sergey.Semin@baikalelectronics.ru

clocksource: Fix MIPS GIC and DW APB Timer for Baikal-T1 SoC support:
Link: https://lore.kernel.org/linux-rtc/20200324174325.14213-1-Sergey.Semin@baikalelectronics.ru
Link: https://lore.kernel.org/linux-rtc/20200506214107.25956-1-Sergey.Semin@baikalelectronics.ru
Link: https://lore.kernel.org/linux-rtc/20200521005321.12129-1-Sergey.Semin@baikalelectronics.ru

Changelog prev:
- Add yaml-based bindings file for MIPS CDMM dt-node.
- Convert mti,mips-cpc to DT schema.
- Use a shorter summary describing the bindings modification patches.
- Rearrange the SoBs with adding Alexey' co-development tag.
- Lowercase the hex numbers in the dt-bindings.

Changelog v2:
- Resend.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <maz@kernel.org>
Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org

Serge Semin (6):
  dt-bindings: power: Convert mti,mips-cpc to DT schema
  dt-bindings: interrupt-controller: Convert mti,gic to DT schema
  dt-bindings: bus: Add MIPS CDMM controller
  mips: cdmm: Add mti,mips-cdmm dtb node support
  bus: cdmm: Add MIPS R5 arch support
  MAINTAINERS: Add maintainers for MIPS core drivers

 .../bindings/bus/mti,mips-cdmm.yaml           |  35 +++++
 .../interrupt-controller/mips-gic.txt         |  67 --------
 .../interrupt-controller/mti,gic.yaml         | 148 ++++++++++++++++++
 .../bindings/power/mti,mips-cpc.txt           |   8 -
 .../bindings/power/mti,mips-cpc.yaml          |  35 +++++
 MAINTAINERS                                   |  10 ++
 drivers/bus/Kconfig                           |   2 +-
 drivers/bus/mips_cdmm.c                       |  15 ++
 8 files changed, 244 insertions(+), 76 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/bus/mti,mips-cdmm.yaml
 delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml
 delete mode 100644 Documentation/devicetree/bindings/power/mti,mips-cpc.txt
 create mode 100644 Documentation/devicetree/bindings/power/mti,mips-cpc.yaml

-- 
2.26.2

[PATCH v2 2/6] dt-bindings: interrupt-controller: Convert mti,gic to DT schema

[Serge Semin]

Modern device tree bindings are supposed to be created as YAML-files
in accordance with DT schema. This commit replaces MIPS GIC legacy bare
text binding with YAML file. As before the binding file states that the
corresponding dts node is supposed to be compatible with MIPS Global
Interrupt Controller indicated by the "mti,gic" compatible string and
to provide a mandatory interrupt-controller and '#interrupt-cells'
properties. There might be optional registers memory range,
"mti,reserved-cpu-vectors" and "mti,reserved-ipi-vectors" properties
specified.

MIPS GIC also includes a free-running global timer, per-CPU count/compare
timers, and a watchdog. Since currently the GIC Timer is only supported the
DT schema expects an IRQ and clock-phandler charged timer sub-node with
"mti,mips-gic-timer" compatible string.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Rob Herring <robh@kernel.org>

---

I don't really know who is the corresponding driver maintainer, so I
added Paul to the maintainers property since he used to be looking for the
MIPS arch and Thomas looking after it now. Any idea what email should be
specified there instead?

Changelog prev:
- Since timer sub-node has no unit-address, the node shouldn't be named
  with one. So alter the MIPS GIC bindings to have a pure "timer"
  sub-node.
- Discard allOf: [ $ref: /schemas/interrupt-controller.yaml# ].
- Since it's a conversion patch use GPL-2.0-only SPDX header.
---
 .../interrupt-controller/mips-gic.txt         |  67 --------
 .../interrupt-controller/mti,gic.yaml         | 148 ++++++++++++++++++
 2 files changed, 148 insertions(+), 67 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml

diff --git a/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt b/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
deleted file mode 100644
index 173595305e26..000000000000
--- a/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
+++ /dev/null
@@ -1,67 +0,0 @@
-MIPS Global Interrupt Controller (GIC)
-
-The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
-It also supports local (per-processor) interrupts and software-generated
-interrupts which can be used as IPIs.  The GIC also includes a free-running
-global timer, per-CPU count/compare timers, and a watchdog.
-
-Required properties:
-- compatible : Should be "mti,gic".
-- interrupt-controller : Identifies the node as an interrupt controller
-- #interrupt-cells : Specifies the number of cells needed to encode an
-  interrupt specifier.  Should be 3.
-  - The first cell is the type of interrupt, local or shared.
-    See <include/dt-bindings/interrupt-controller/mips-gic.h>.
-  - The second cell is the GIC interrupt number.
-  - The third cell encodes the interrupt flags.
-    See <include/dt-bindings/interrupt-controller/irq.h> for a list of valid
-    flags.
-
-Optional properties:
-- reg : Base address and length of the GIC registers.  If not present,
-  the base address reported by the hardware GCR_GIC_BASE will be used.
-- mti,reserved-cpu-vectors : Specifies the list of CPU interrupt vectors
-  to which the GIC may not route interrupts.  Valid values are 2 - 7.
-  This property is ignored if the CPU is started in EIC mode.
-- mti,reserved-ipi-vectors : Specifies the range of GIC interrupts that are
-  reserved for IPIs.
-  It accepts 2 values, the 1st is the starting interrupt and the 2nd is the size
-  of the reserved range.
-  If not specified, the driver will allocate the last 2 * number of VPEs in the
-  system.
-
-Required properties for timer sub-node:
-- compatible : Should be "mti,gic-timer".
-- interrupts : Interrupt for the GIC local timer.
-
-Optional properties for timer sub-node:
-- clocks : GIC timer operating clock.
-- clock-frequency : Clock frequency at which the GIC timers operate.
-
-Note that one of clocks or clock-frequency must be specified.
-
-Example:
-
-	gic: interrupt-controller@1bdc0000 {
-		compatible = "mti,gic";
-		reg = <0x1bdc0000 0x20000>;
-
-		interrupt-controller;
-		#interrupt-cells = <3>;
-
-		mti,reserved-cpu-vectors = <7>;
-		mti,reserved-ipi-vectors = <40 8>;
-
-		timer {
-			compatible = "mti,gic-timer";
-			interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
-			clock-frequency = <50000000>;
-		};
-	};
-
-	uart@18101400 {
-		...
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
-		...
-	};
diff --git a/Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml b/Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml
new file mode 100644
index 000000000000..9f0eb3addac4
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml
@@ -0,0 +1,148 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MIPS Global Interrupt Controller
+
+maintainers:
+  - Paul Burton <paulburton@kernel.org>
+  - Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+
+description: |
+  The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
+  It also supports local (per-processor) interrupts and software-generated
+  interrupts which can be used as IPIs. The GIC also includes a free-running
+  global timer, per-CPU count/compare timers, and a watchdog.
+
+properties:
+  compatible:
+    const: mti,gic
+
+  "#interrupt-cells":
+    const: 3
+    description: |
+      The 1st cell is the type of interrupt: local or shared defined in the
+      file 'dt-bindings/interrupt-controller/mips-gic.h'. The 2nd cell is the
+      GIC interrupt number. The 3d cell encodes the interrupt flags setting up
+      the IRQ trigger modes, which are defined in the file
+      'dt-bindings/interrupt-controller/irq.h'.
+
+  reg:
+    description: |
+      Base address and length of the GIC registers space. If not present,
+      the base address reported by the hardware GCR_GIC_BASE will be used.
+    maxItems: 1
+
+  interrupt-controller: true
+
+  mti,reserved-cpu-vectors:
+    description: |
+      Specifies the list of CPU interrupt vectors to which the GIC may not
+      route interrupts. This property is ignored if the CPU is started in EIC
+      mode.
+    allOf:
+      - $ref: /schemas/types.yaml#definitions/uint32-array
+      - minItems: 1
+        maxItems: 6
+        uniqueItems: true
+        items:
+          minimum: 2
+          maximum: 7
+
+  mti,reserved-ipi-vectors:
+    description: |
+      Specifies the range of GIC interrupts that are reserved for IPIs.
+      It accepts two values: the 1st is the starting interrupt and the 2nd is
+      the size of the reserved range. If not specified, the driver will
+      allocate the last (2 * number of VPEs in the system).
+    allOf:
+      - $ref: /schemas/types.yaml#definitions/uint32-array
+      - items:
+          - minimum: 0
+            maximum: 254
+          - minimum: 2
+            maximum: 254
+
+  timer:
+    type: object
+    description: |
+      MIPS GIC includes a free-running global timer, per-CPU count/compare
+      timers, and a watchdog. Currently only the GIC Timer is supported.
+    properties:
+      compatible:
+        const: mti,gic-timer
+
+      interrupts:
+        description: |
+          Interrupt for the GIC local timer, so normally it's suppose to be of
+          <GIC_LOCAL X IRQ_TYPE_NONE> format.
+        maxItems: 1
+
+      clocks:
+        maxItems: 1
+
+      clock-frequency: true
+
+    required:
+      - compatible
+      - interrupts
+
+    oneOf:
+      - required:
+          - clocks
+      - required:
+          - clock-frequency
+
+    additionalProperties: false
+
+unevaluatedProperties: false
+
+required:
+  - compatible
+  - "#interrupt-cells"
+  - interrupt-controller
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/mips-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    interrupt-controller@1bdc0000 {
+      compatible = "mti,gic";
+      reg = <0x1bdc0000 0x20000>;
+      interrupt-controller;
+      #interrupt-cells = <3>;
+      mti,reserved-cpu-vectors = <7>;
+      mti,reserved-ipi-vectors = <40 8>;
+
+      timer {
+        compatible = "mti,gic-timer";
+        interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
+        clock-frequency = <50000000>;
+      };
+    };
+  - |
+    #include <dt-bindings/interrupt-controller/mips-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    interrupt-controller@1bdc0000 {
+      compatible = "mti,gic";
+      reg = <0x1bdc0000 0x20000>;
+      interrupt-controller;
+      #interrupt-cells = <3>;
+
+      timer {
+        compatible = "mti,gic-timer";
+        interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
+        clocks = <&cpu_pll>;
+      };
+    };
+  - |
+    interrupt-controller {
+      compatible = "mti,gic";
+      interrupt-controller;
+      #interrupt-cells = <3>;
+    };
+...
-- 
2.26.2