From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F460C2D0F4 for ; Wed, 1 Apr 2020 10:19:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 06C8620787 for ; Wed, 1 Apr 2020 10:19:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731792AbgDAKTo (ORCPT ); Wed, 1 Apr 2020 06:19:44 -0400 Received: from mail.baikalelectronics.com ([87.245.175.226]:56124 "EHLO mail.baikalelectronics.ru" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727308AbgDAKTo (ORCPT ); Wed, 1 Apr 2020 06:19:44 -0400 Received: from localhost (unknown [127.0.0.1]) by mail.baikalelectronics.ru (Postfix) with ESMTP id 6F0808030776; Wed, 1 Apr 2020 10:19:39 +0000 (UTC) X-Virus-Scanned: amavisd-new at baikalelectronics.ru Received: from mail.baikalelectronics.ru ([127.0.0.1]) by localhost (mail.baikalelectronics.ru [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id j0jbirOyuJqB; Wed, 1 Apr 2020 13:19:38 +0300 (MSK) Date: Wed, 1 Apr 2020 13:19:31 +0300 From: Sergey Semin To: Rob Herring CC: Thomas Gleixner , Jason Cooper , Marc Zyngier , Mark Rutland , Alexey Malahov , Thomas Bogendoerfer , Paul Burton , Ralf Baechle , Alessandro Zummo , Alexandre Belloni , Daniel Lezcano , Arnd Bergmann , Andy Shevchenko , , , Subject: Re: [PATCH v2 2/6] dt-bindings: interrupt-controller: Convert mti,gic to DT schema Message-ID: <20200401101930.3lk4t6wk6j5ne6ay@ubsrv2.baikal.int> References: <20200306125622.839ED80307C4@mail.baikalelectronics.ru> <20200324174325.14213-1-Sergey.Semin@baikalelectronics.ru> <20200324174325.14213-3-Sergey.Semin@baikalelectronics.ru> <20200331210248.GA27684@bogus> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20200331210248.GA27684@bogus> X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Mar 31, 2020 at 03:02:48PM -0600, Rob Herring wrote: > On Tue, Mar 24, 2020 at 08:43:21PM +0300, Sergey.Semin@baikalelectronics.ru wrote: > > From: Serge Semin > > > > Modern device tree bindings are supposed to be created as YAML-files > > in accordance with DT schema. This commit replaces MIPS GIC legacy bare > > text binding with YAML file. As before the binding file states that the > > corresponding dts node is supposed to be compatible with MIPS Global > > Interrupt Controller indicated by the "mti,gic" compatible string and > > to provide a mandatory interrupt-controller and '#interrupt-cells' > > properties. There might be optional registers memory range, > > "mti,reserved-cpu-vectors" and "mti,reserved-ipi-vectors" properties > > specified. > > > > MIPS GIC also includes a free-running global timer, per-CPU count/compare > > timers, and a watchdog. Since currently the GIC Timer is only supported the > > DT schema expects an IRQ and clock-phandler charged timer sub-node with > > "mti,mips-gic-timer" compatible string. > > > > Signed-off-by: Serge Semin > > Cc: Alexey Malahov > > Cc: Thomas Bogendoerfer > > Cc: Paul Burton > > Cc: Ralf Baechle > > Cc: Alessandro Zummo > > Cc: Alexandre Belloni > > Cc: Daniel Lezcano > > Cc: Thomas Gleixner > > Cc: Arnd Bergmann > > Cc: Andy Shevchenko > > Cc: Rob Herring > > Cc: Mark Rutland > > Cc: devicetree@vger.kernel.org > > Cc: linux-rtc@vger.kernel.org > > > > --- > > > > I don't really know who is the corresponding driver maintainer, so I > > added to the maintainers schema Paul since he used to be looking for the > > MIPS arch and Thomas looking after it now. Any idea what email should be > > specified there instead? > > > > Similarly to the previous patch the "oneOf: - required: ..." pattern isn't > > working here. Supposedly due to the script' dtschema/lib.py > > interrupts/interrupts-extended fixup. > > --- > > .../interrupt-controller/mips-gic.txt | 67 -------- > > .../interrupt-controller/mti,gic.yaml | 152 ++++++++++++++++++ > > 2 files changed, 152 insertions(+), 67 deletions(-) > > delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt > > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml > > > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt b/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt > > deleted file mode 100644 > > index 173595305e26..000000000000 > > --- a/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt > > +++ /dev/null > > @@ -1,67 +0,0 @@ > > -MIPS Global Interrupt Controller (GIC) > > - > > -The MIPS GIC routes external interrupts to individual VPEs and IRQ pins. > > -It also supports local (per-processor) interrupts and software-generated > > -interrupts which can be used as IPIs. The GIC also includes a free-running > > -global timer, per-CPU count/compare timers, and a watchdog. > > - > > -Required properties: > > -- compatible : Should be "mti,gic". > > -- interrupt-controller : Identifies the node as an interrupt controller > > -- #interrupt-cells : Specifies the number of cells needed to encode an > > - interrupt specifier. Should be 3. > > - - The first cell is the type of interrupt, local or shared. > > - See . > > - - The second cell is the GIC interrupt number. > > - - The third cell encodes the interrupt flags. > > - See for a list of valid > > - flags. > > - > > -Optional properties: > > -- reg : Base address and length of the GIC registers. If not present, > > - the base address reported by the hardware GCR_GIC_BASE will be used. > > -- mti,reserved-cpu-vectors : Specifies the list of CPU interrupt vectors > > - to which the GIC may not route interrupts. Valid values are 2 - 7. > > - This property is ignored if the CPU is started in EIC mode. > > -- mti,reserved-ipi-vectors : Specifies the range of GIC interrupts that are > > - reserved for IPIs. > > - It accepts 2 values, the 1st is the starting interrupt and the 2nd is the size > > - of the reserved range. > > - If not specified, the driver will allocate the last 2 * number of VPEs in the > > - system. > > - > > -Required properties for timer sub-node: > > -- compatible : Should be "mti,gic-timer". > > -- interrupts : Interrupt for the GIC local timer. > > - > > -Optional properties for timer sub-node: > > -- clocks : GIC timer operating clock. > > -- clock-frequency : Clock frequency at which the GIC timers operate. > > - > > -Note that one of clocks or clock-frequency must be specified. > > - > > -Example: > > - > > - gic: interrupt-controller@1bdc0000 { > > - compatible = "mti,gic"; > > - reg = <0x1bdc0000 0x20000>; > > - > > - interrupt-controller; > > - #interrupt-cells = <3>; > > - > > - mti,reserved-cpu-vectors = <7>; > > - mti,reserved-ipi-vectors = <40 8>; > > - > > - timer { > > - compatible = "mti,gic-timer"; > > - interrupts = ; > > - clock-frequency = <50000000>; > > - }; > > - }; > > - > > - uart@18101400 { > > - ... > > - interrupt-parent = <&gic>; > > - interrupts = ; > > - ... > > - }; > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml b/Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml > > new file mode 100644 > > index 000000000000..1e47c0cdc231 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml > > @@ -0,0 +1,152 @@ > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > Do you have rights to add BSD? > My manager said we can submitted the DT schema bindings under both GPL and BSD licenses. Though I don't know what license was of the legacy binding file. BTW Rob, you ask about the license very often whether I set pure GPL-2.0 or dual-license header. Just wondering is it some kind of protocol to make sure a submitter has got proper rights to submit the binding? > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: MIPS Global Interrupt Controller > > + > > +maintainers: > > + - Paul Burton > > + - Thomas Bogendoerfer > > + > > +description: | > > + The MIPS GIC routes external interrupts to individual VPEs and IRQ pins. > > + It also supports local (per-processor) interrupts and software-generated > > + interrupts which can be used as IPIs. The GIC also includes a free-running > > + global timer, per-CPU count/compare timers, and a watchdog. > > + > > +allOf: > > + - $ref: /schemas/interrupt-controller.yaml# > > Drop this. > Ok. > > + > > +properties: > > + compatible: > > + const: mti,gic > > + > > + "#interrupt-cells": > > + const: 3 > > + description: | > > + The 1st cell is the type of interrupt: local or shared defined in the > > + file 'dt-bindings/interrupt-controller/mips-gic.h'. The 2nd cell is the > > + GIC interrupt number. The 3d cell encodes the interrupt flags setting up > > + the IRQ trigger modes, which are defined in the file > > + 'dt-bindings/interrupt-controller/irq.h'. > > + > > + reg: > > + description: | > > + Base address and length of the GIC registers space. If not present, > > + the base address reported by the hardware GCR_GIC_BASE will be used. > > + maxItems: 1 > > + > > + interrupt-controller: true > > + > > + mti,reserved-cpu-vectors: > > + description: | > > + Specifies the list of CPU interrupt vectors to which the GIC may not > > + route interrupts. This property is ignored if the CPU is started in EIC > > + mode. > > + allOf: > > + - $ref: /schemas/types.yaml#definitions/uint32-array > > + - minItems: 1 > > + maxItems: 6 > > + uniqueItems: true > > + items: > > + minimum: 2 > > + maximum: 7 > > + > > + mti,reserved-ipi-vectors: > > + description: | > > + Specifies the range of GIC interrupts that are reserved for IPIs. > > + It accepts two values: the 1st is the starting interrupt and the 2nd is > > + the size of the reserved range. If not specified, the driver will > > + allocate the last (2 * number of VPEs in the system). > > + allOf: > > + - $ref: /schemas/types.yaml#definitions/uint32-array > > + - items: > > + - minimum: 0 > > + maximum: 254 > > + - minimum: 2 > > + maximum: 254 > > + > > +patternProperties: > > + "^timer(@[0-9a-f]+)?$": > > If you have an unit-address, then there should be a 'reg' property. > > Seems like this can be just 'timer'? > Ok. reg property isn't supported by the timer sub-node. So I'll make it to be just "timer" node with no unit-address number. -Sergey > > + type: object > > + description: | > > + MIPS GIC includes a free-running global timer, per-CPU count/compare > > + timers, and a watchdog. Currently only the GIC Timer is supported. > > + properties: > > + compatible: > > + const: mti,gic-timer > > + > > + interrupts: > > + description: | > > + Interrupt for the GIC local timer, so normally it's suppose to be of > > + format. > > + maxItems: 1 > > + > > + clocks: > > + maxItems: 1 > > + > > + clock-frequency: true > > + > > + required: > > + - compatible > > + - interrupts > > + > > + oneOf: > > + - required: > > + - clocks > > + - required: > > + - clock-frequency > > + > > + additionalProperties: false > > + > > +unevaluatedProperties: false > > + > > +required: > > + - compatible > > + - "#interrupt-cells" > > + - interrupt-controller > > + > > +examples: > > + - | > > + #include > > + #include > > + > > + interrupt-controller@1bdc0000 { > > + compatible = "mti,gic"; > > + reg = <0x1bdc0000 0x20000>; > > + interrupt-controller; > > + #interrupt-cells = <3>; > > + mti,reserved-cpu-vectors = <7>; > > + mti,reserved-ipi-vectors = <40 8>; > > + > > + timer { > > + compatible = "mti,gic-timer"; > > + interrupts = ; > > + clock-frequency = <50000000>; > > + }; > > + }; > > + - | > > + #include > > + #include > > + > > + interrupt-controller@1bdc0000 { > > + compatible = "mti,gic"; > > + reg = <0x1bdc0000 0x20000>; > > + interrupt-controller; > > + #interrupt-cells = <3>; > > + > > + timer { > > + compatible = "mti,gic-timer"; > > + interrupts = ; > > + clocks = <&cpu_pll>; > > + }; > > + }; > > + - | > > + interrupt-controller { > > + compatible = "mti,gic"; > > + interrupt-controller; > > + #interrupt-cells = <3>; > > + }; > > +... > > -- > > 2.25.1 > >