From: Robert Richter <rrichter@marvell.com>
To: Sherry Sun <sherry.sun@nxp.com>
Cc: "bp@alien8.de" <bp@alien8.de>,
"mchehab@kernel.org" <mchehab@kernel.org>,
"tony.luck@intel.com" <tony.luck@intel.com>,
"james.morse@arm.com" <james.morse@arm.com>,
"michal.simek@xilinx.com" <michal.simek@xilinx.com>,
"manish.narani@xilinx.com" <manish.narani@xilinx.com>,
"linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
dl-linux-imx <linux-imx@nxp.com>, Frank Li <frank.li@nxp.com>
Subject: Re: [patch v3 3/4] EDAC: synopsys: Add edac driver support for i.MX8MP
Date: Thu, 2 Apr 2020 13:17:09 +0200 [thread overview]
Message-ID: <20200402111709.qr7zpo5o5vrwh5kb@rric.localdomain> (raw)
In-Reply-To: <VI1PR04MB4960985DD2A4F0CA68063D9592C60@VI1PR04MB4960.eurprd04.prod.outlook.com>
On 02.04.20 09:06:27, Sherry Sun wrote:
> > From: Robert Richter <rrichter@marvell.com>
> > On 02.04.20 09:20:32, Sherry Sun wrote:
> > > +static void enable_intr_imx8mp(struct synps_edac_priv *priv) {
> > > + int regval;
> > > +
> > > + regval = readl(priv->baseaddr + ECC_CLR_OFST);
> > > + regval |= (DDR_CE_INTR_EN_MASK | DDR_UE_INTR_EN_MASK);
> > > + writel(regval, priv->baseaddr + ECC_CLR_OFST); }
> > > +
> > > +static void disable_intr_imx8mp(struct synps_edac_priv *priv) {
> > > + int regval;
> > > +
> > > + regval = readl(priv->baseaddr + ECC_CLR_OFST);
> > > + regval &= ~(DDR_CE_INTR_EN_MASK | DDR_UE_INTR_EN_MASK);
> > > + writel(regval, priv->baseaddr + ECC_CLR_OFST); }
> > > +
> > > +/* Interrupt Handler for ECC interrupts on imx8mp platform. */ static
> > > +irqreturn_t intr_handler_imx8mp(int irq, void *dev_id) {
> > > + const struct synps_platform_data *p_data;
> > > + struct mem_ctl_info *mci = dev_id;
> > > + struct synps_edac_priv *priv;
> > > + int status, regval;
> > > +
> > > + priv = mci->pvt_info;
> > > + p_data = priv->p_data;
> > > +
> > > + regval = readl(priv->baseaddr + ECC_STAT_OFST);
> > > + if (!(regval & ECC_INTR_MASK))
> > > + return IRQ_NONE;
> > > +
> > > + status = p_data->get_error_info(priv);
> > > + if (status)
> > > + return IRQ_NONE;
> > > +
> > > + priv->ce_cnt += priv->stat.ce_cnt;
> > > + priv->ue_cnt += priv->stat.ue_cnt;
> > > + handle_error(mci, &priv->stat);
> > > +
> > > + edac_dbg(3, "Total error count CE %d UE %d\n",
> > > + priv->ce_cnt, priv->ue_cnt);
> > > + enable_intr_imx8mp(priv);
> >
> > Why do you enable interrupts here?
>
> Because zynqmp_get_error_info() wrote 0 to ECC_CLR_OFST, so here have to re-enable the interrupts.
This does not seem to be the right place for it.
> As said in the commit, the main difference between ZynqMP and i.MX8MP ddr controller is the interrupt registers.
> ZynqMP use DDR QOS Interrupt registers, but i.MX8MP use ECC_CLR_OFST Register(bit8 and bit9) to enable/disable the ce/ue interrupts.
>
> In zynqmp_get_error_info(), Zynqmp wrote 0 to ECC_CLR_OFST register to clear CE/UE error flags and counts, it has no effect on Zynqmp interrupts.
> But for i.MX8MP, wirte 0 to ECC_CLR_OFST will disable i.MX8MP CE/UE interrupt, so need re-enable the interrupts.
All this shows one more time there should be separate handlers. You
should get rid most callbacks in struct synps_platform_data and
instead have separate probe functions for both flavors that share
common code.
-Robert
next prev parent reply other threads:[~2020-04-02 11:17 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-02 1:20 [patch v3 0/4] Add edac driver for i.MX8MP based on synopsys edac driver Sherry Sun
2020-04-02 1:20 ` [patch v3 1/4] dt-bindings: memory-controllers: Add i.MX8MP DDRC binding doc Sherry Sun
2020-04-02 1:20 ` [patch v3 2/4] EDAC: Add synopsys edac driver support for i.MX8MP Sherry Sun
2020-04-02 1:20 ` [patch v3 3/4] EDAC: synopsys: Add " Sherry Sun
2020-04-02 7:22 ` Robert Richter
2020-04-02 9:06 ` Sherry Sun
2020-04-02 11:17 ` Robert Richter [this message]
2020-04-02 13:09 ` Sherry Sun
2020-04-08 6:40 ` Robert Richter
2020-04-02 1:20 ` [patch v3 4/4] EDAC: synopsys: Add useful debug and output information for 64bit systems Sherry Sun
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