From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C00D7C43331 for ; Thu, 2 Apr 2020 14:59:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9DFC72072E for ; Thu, 2 Apr 2020 14:59:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389190AbgDBO7t (ORCPT ); Thu, 2 Apr 2020 10:59:49 -0400 Received: from [103.51.140.103] ([103.51.140.103]:37766 "EHLO E6440.gar.corp.intel.com" rhost-flags-FAIL-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S2388782AbgDBO7t (ORCPT ); Thu, 2 Apr 2020 10:59:49 -0400 X-Greylist: delayed 499 seconds by postgrey-1.27 at vger.kernel.org; Thu, 02 Apr 2020 10:59:48 EDT Received: from E6440.gar.corp.intel.com (localhost [127.0.0.1]) by E6440.gar.corp.intel.com (Postfix) with ESMTP id 31FF9C05C7; Thu, 2 Apr 2020 22:48:07 +0800 (CST) From: Harry Pan To: LKML Cc: gs0622@gmail.com, Harry Pan , Alexander Shishkin , Arnaldo Carvalho de Melo , Borislav Petkov , "H. Peter Anvin" , Ingo Molnar , Jiri Olsa , Mark Rutland , Namhyung Kim , Peter Zijlstra , Thomas Gleixner , x86@kernel.org Subject: [PATCH] perf/x86/cstate: Add Jasper Lake CPU support Date: Thu, 2 Apr 2020 22:48:05 +0800 Message-Id: <20200402224802.1.Ic02e891daac41303aed1f2fc6c64f6110edd27bd@changeid> X-Mailer: git-send-email 2.24.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Jasper Lake processor is Tremont microarchitecture, we can reuse the glm_cstates table of Goldmont and Goldmont Plus to enable the C-states residency profiling. Signed-off-by: Harry Pan --- arch/x86/events/intel/cstate.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c index e4aa20c0426f..442e1ed4acd4 100644 --- a/arch/x86/events/intel/cstate.c +++ b/arch/x86/events/intel/cstate.c @@ -643,6 +643,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = { X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_PLUS, &glm_cstates), X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, &glm_cstates), X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT, &glm_cstates), + X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L, &glm_cstates), X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L, &icl_cstates), X86_MATCH_INTEL_FAM6_MODEL(ICELAKE, &icl_cstates), -- 2.24.1