Re: [PATCH 2/2] x86/resctrl: Support CPUID enumeration of MBM counter width

[Fenghua Yu <fenghua.yu@intel.com>]

On Wed, Apr 01, 2020 at 10:51:02AM -0700, Reinette Chatre wrote:
> The original Memory Bandwidth Monitoring (MBM) architectural
> definition defines counters of up to 62 bits in the
> IA32_QM_CTR MSR while the first-generation MBM implementation
> uses statically defined 24 bit counters.
> 
> @@ -856,6 +856,8 @@ static void init_speculation_control(struct cpuinfo_x86 *c)
>  
>  static void init_cqm(struct cpuinfo_x86 *c)
>  {
> +	c->x86_cache_mbm_width_offset = -1;
> +
>  	if (!cpu_has(c, X86_FEATURE_CQM_LLC)) {
>  		c->x86_cache_max_rmid  = -1;
>  		c->x86_cache_occ_scale = -1;
> @@ -875,6 +877,9 @@ static void init_cqm(struct cpuinfo_x86 *c)
>  
>  		c->x86_cache_max_rmid  = ecx;
>  		c->x86_cache_occ_scale = ebx;
> +		/* EAX contents is only defined for Intel CPUs */
> +		if (c->x86_vendor == X86_VENDOR_INTEL)
> +			c->x86_cache_mbm_width_offset = eax & 0xff;

Is it reliable to read eax which is reserved on older platforms that
don't support the feature?

Seems the code assumes the reserved eax is 0 on those platforms. Is it
reliable?

>  int rdt_get_mon_l3_config(struct rdt_resource *r)
>  {
> +	unsigned int mbm_offset = boot_cpu_data.x86_cache_mbm_width_offset;
>  	unsigned int cl_size = boot_cpu_data.x86_cache_size;
>  	int ret;
>  
>  	r->mon_scale = boot_cpu_data.x86_cache_occ_scale;
>  	r->num_rmid = boot_cpu_data.x86_cache_max_rmid + 1;
> -	r->mbm_width = MBM_CNTR_WIDTH;
> +	r->mbm_width = MBM_CNTR_WIDTH_BASE;
> +
> +	if (mbm_offset > 0 && mbm_offset <= MBM_CNTR_WIDTH_OFFSET_MAX)
> +		r->mbm_width += mbm_offset;
> +	else if (mbm_offset > MBM_CNTR_WIDTH_OFFSET_MAX)
> +		pr_warn("Ignoring impossible MBM counter offset\n");
>  

Thanks.

-Fenghua