From: Will Deacon <will@kernel.org>
To: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: mark.rutland@arm.com, catalin.marinas@arm.com,
linux-kernel@vger.kernel.org, james.morse@arm.com,
maz@kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 0/5] arm64: Add workaround for Cortex-A77 erratum 1542418
Date: Wed, 8 Apr 2020 11:09:59 +0100 [thread overview]
Message-ID: <20200408100956.GA32568@willie-the-truck> (raw)
In-Reply-To: <20191120191854.GG4799@willie-the-truck>
Hi Suzuki,
On Wed, Nov 20, 2019 at 07:18:55PM +0000, Will Deacon wrote:
> On Fri, Nov 15, 2019 at 01:14:07AM +0000, Suzuki K Poulose wrote:
> > On 11/14/2019 04:39 PM, Will Deacon wrote:
> > > addr: B foo
> > >
> > > and another CPU writes out a new function:
> > >
> > > bar:
> > > insn0
> > > ...
> > > insnN
> > >
> > > before doing any necessary maintenance and then patches the original
> > > branch to:
> > >
> > > addr: B bar
> > >
> > > The idea is that a concurrently executing CPU could mispredict the original
> > > branch to point at 'bar', fetch the instructions before they've been written
> > > out and then confirm the prediction by looking at the newly written branch
> > > instruction. Even without the prefetch-speculation-protection, that's
> > > fairly difficult to achieve in practice: you'd need to be doing something
> > > like reusing memory to hold the instructions so that the initial
> > > misprediction occurs.
> > >
> > > How does A77 stop this from occurring when the ASID is not reallocated (e.g.
> > > the example above)? Is the MOP cache flushed somehow?
> >
> > IIUC, The MOP cache is flushed on I-cache invalidate, thus it is fine.
>
> Hmm, so this is interesting. Does that mean we could do a local I-cache
> invalidation in check_and_switch_context() at the same as doing the local
> TLBI after a rollover?
>
> I still don't grok the failure case, though, because assuming A77 has IDC=0,
> then won't you see the I-cache maintenance from userspace anyway?
Please could you explain why the userspace I-cache maintenance doesn't
resolve the issue here?
Thanks,
Will
prev parent reply other threads:[~2020-04-08 10:10 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-14 14:59 [PATCH 0/5] arm64: Add workaround for Cortex-A77 erratum 1542418 Suzuki K Poulose
2019-11-14 14:59 ` [PATCH 1/5] arm64: Add MIDR encoding for Arm Cortex-A77 Suzuki K Poulose
2019-11-14 14:59 ` [PATCH 2/5] arm64: mm: Workaround Cortex-A77 erratum 1542418 on ASID rollover Suzuki K Poulose
2019-11-14 14:59 ` [PATCH 3/5] arm64: Workaround Cortex-A77 erratum 1542418 on boot due to kexec Suzuki K Poulose
2019-11-14 14:59 ` [PATCH 4/5] KVM: arm64: Workaround Cortex-A77 erratum 1542418 on VMID rollover Suzuki K Poulose
2019-11-14 14:59 ` [PATCH 5/5] KVM: arm/arm64: Don't invoke defacto-CnP on first run Suzuki K Poulose
2019-11-14 16:39 ` [PATCH 0/5] arm64: Add workaround for Cortex-A77 erratum 1542418 Will Deacon
2019-11-15 1:14 ` Suzuki K Poulose
2019-11-20 19:18 ` Will Deacon
2020-04-08 10:09 ` Will Deacon [this message]
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