From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5112AC2BBC7 for ; Sat, 11 Apr 2020 23:13:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2AE0D20708 for ; Sat, 11 Apr 2020 23:13:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1586646801; bh=4preyET11OEyv7wXhx2hGsIb1dpvel1gneQuWfIGOcc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=GmUvkBdcqZ0/04Tb5BIg7gQX/pmMiAnsVJtJKKl0VnfZnAtmMrwFveVpgqVZ8LU2a QdizfvyGxXjtQeKoWpX6gIBj20209G3S0h7AbsxD9mW8jM6PUqbGpsfaO2nSPTt/gW YfB4kl/njUdf3KqaPYcPoXvVIZAAmAEKYOCcUCgs= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730398AbgDKXNT (ORCPT ); Sat, 11 Apr 2020 19:13:19 -0400 Received: from mail.kernel.org ([198.145.29.99]:53856 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730239AbgDKXNC (ORCPT ); Sat, 11 Apr 2020 19:13:02 -0400 Received: from sasha-vm.mshome.net (c-73-47-72-35.hsd1.nh.comcast.net [73.47.72.35]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 02E1721841; Sat, 11 Apr 2020 23:13:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1586646782; bh=4preyET11OEyv7wXhx2hGsIb1dpvel1gneQuWfIGOcc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XNn1k67QjoMovZ7bva4P7G/CI92EtXYcTbkV1zR0l7pi0qcFaYThmUoW8HNN8u4uv wWbCfs5x5/fknZo3fMb3mvoxRa/u2U5gwp2hOMnpqxlo87tPxE36mDuthEI/aPyYF0 5FQlL2CHpNn/6bSVnOt2JZ9wUwih0xJQJgG9UQi8= From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Jordan Crouse , Eric Anholt , Rob Clark , Sasha Levin , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH AUTOSEL 4.19 48/66] drm/msm/a5xx: Always set an OPP supported hardware value Date: Sat, 11 Apr 2020 19:11:45 -0400 Message-Id: <20200411231203.25933-48-sashal@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200411231203.25933-1-sashal@kernel.org> References: <20200411231203.25933-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Jordan Crouse [ Upstream commit 0478b4fc5f37f4d494245fe7bcce3f531cf380e9 ] If the opp table specifies opp-supported-hw as a property but the driver has not set a supported hardware value the OPP subsystem will reject all the table entries. Set a "default" value that will match the default table entries but not conflict with any possible real bin values. Also fix a small memory leak and free the buffer allocated by nvmem_cell_read(). Signed-off-by: Jordan Crouse Reviewed-by: Eric Anholt Signed-off-by: Rob Clark Signed-off-by: Sasha Levin --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 27 ++++++++++++++++++++------- 1 file changed, 20 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index ba6f3c14495c0..dd298abc5f393 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -1474,18 +1474,31 @@ static const struct adreno_gpu_funcs funcs = { static void check_speed_bin(struct device *dev) { struct nvmem_cell *cell; - u32 bin, val; + u32 val; + + /* + * If the OPP table specifies a opp-supported-hw property then we have + * to set something with dev_pm_opp_set_supported_hw() or the table + * doesn't get populated so pick an arbitrary value that should + * ensure the default frequencies are selected but not conflict with any + * actual bins + */ + val = 0x80; cell = nvmem_cell_get(dev, "speed_bin"); - /* If a nvmem cell isn't defined, nothing to do */ - if (IS_ERR(cell)) - return; + if (!IS_ERR(cell)) { + void *buf = nvmem_cell_read(cell, NULL); + + if (!IS_ERR(buf)) { + u8 bin = *((u8 *) buf); - bin = *((u32 *) nvmem_cell_read(cell, NULL)); - nvmem_cell_put(cell); + val = (1 << bin); + kfree(buf); + } - val = (1 << bin); + nvmem_cell_put(cell); + } dev_pm_opp_set_supported_hw(dev, &val, 1); } -- 2.20.1