From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA246C2BA19 for ; Wed, 15 Apr 2020 12:10:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A9DF1206F9 for ; Wed, 15 Apr 2020 12:10:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1586952633; bh=x1Q+kvGfO54ewQSFDZp8wBouTouHngWFqa2kQ/WTrT8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=y59Ljdm06SlYpZz4k0tXgn8yTAtaceUDFAUBh1JTf/cIxdFiRoed/2aE5Vz3abTtn MK247QhKWbfOVJoPtShQZEC/Iw2K6Pgy4vVHtawR7f4pqbbcZuSV17K7+UhizspMOG V2pu0q2+ZIETn9SUKILljbctCeLAR022j0Sr26wk= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S368535AbgDOMKb (ORCPT ); Wed, 15 Apr 2020 08:10:31 -0400 Received: from mail.kernel.org ([198.145.29.99]:42622 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2897619AbgDOLrT (ORCPT ); Wed, 15 Apr 2020 07:47:19 -0400 Received: from sasha-vm.mshome.net (c-73-47-72-35.hsd1.nh.comcast.net [73.47.72.35]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 502E021569; Wed, 15 Apr 2020 11:47:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1586951237; bh=x1Q+kvGfO54ewQSFDZp8wBouTouHngWFqa2kQ/WTrT8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=L9H2hY/60x+WFIjqDN8Y3JiIRuKzrNF5nxgWkmcZ0yCnVvejYpMr236sJzHf0gCsA KE5E5iUzgXYXQmkQCLXj+mNUpXIltGrmyA1MHaxPWBX8NicuXj65s8hGLzbuhOMjYU enws0/mFtT90WekbGzhNT42Wvb1KUTJHxo313pdk= From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Lucas Stach , Shawn Guo , Sasha Levin , linux-arm-kernel@lists.infradead.org Subject: [PATCH AUTOSEL 4.14 04/30] soc: imx: gpc: fix power up sequencing Date: Wed, 15 Apr 2020 07:46:45 -0400 Message-Id: <20200415114711.15381-4-sashal@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200415114711.15381-1-sashal@kernel.org> References: <20200415114711.15381-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Lucas Stach [ Upstream commit e0ea2d11f8a08ba7066ff897e16c5217215d1e68 ] Currently we wait only until the PGC inverts the isolation setting before disabling the peripheral clocks. This doesn't ensure that the reset is properly propagated through the peripheral devices in the power domain. Wait until the PGC signals that the power up request is done and wait a bit for resets to propagate before disabling the clocks. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo Signed-off-by: Sasha Levin --- drivers/soc/imx/gpc.c | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/soc/imx/gpc.c b/drivers/soc/imx/gpc.c index 3a12123de4662..0e083fe8b893f 100644 --- a/drivers/soc/imx/gpc.c +++ b/drivers/soc/imx/gpc.c @@ -97,8 +97,8 @@ static int imx6_pm_domain_power_off(struct generic_pm_domain *genpd) static int imx6_pm_domain_power_on(struct generic_pm_domain *genpd) { struct imx_pm_domain *pd = to_imx_pm_domain(genpd); - int i, ret, sw, sw2iso; - u32 val; + int i, ret; + u32 val, req; if (pd->supply) { ret = regulator_enable(pd->supply); @@ -117,17 +117,18 @@ static int imx6_pm_domain_power_on(struct generic_pm_domain *genpd) regmap_update_bits(pd->regmap, pd->reg_offs + GPC_PGC_CTRL_OFFS, 0x1, 0x1); - /* Read ISO and ISO2SW power up delays */ - regmap_read(pd->regmap, pd->reg_offs + GPC_PGC_PUPSCR_OFFS, &val); - sw = val & 0x3f; - sw2iso = (val >> 8) & 0x3f; - /* Request GPC to power up domain */ - val = BIT(pd->cntr_pdn_bit + 1); - regmap_update_bits(pd->regmap, GPC_CNTR, val, val); + req = BIT(pd->cntr_pdn_bit + 1); + regmap_update_bits(pd->regmap, GPC_CNTR, req, req); - /* Wait ISO + ISO2SW IPG clock cycles */ - udelay(DIV_ROUND_UP(sw + sw2iso, pd->ipg_rate_mhz)); + /* Wait for the PGC to handle the request */ + ret = regmap_read_poll_timeout(pd->regmap, GPC_CNTR, val, !(val & req), + 1, 50); + if (ret) + pr_err("powerup request on domain %s timed out\n", genpd->name); + + /* Wait for reset to propagate through peripherals */ + usleep_range(5, 10); /* Disable reset clocks for all devices in the domain */ for (i = 0; i < pd->num_clks; i++) @@ -329,6 +330,7 @@ static const struct regmap_config imx_gpc_regmap_config = { .rd_table = &access_table, .wr_table = &access_table, .max_register = 0x2ac, + .fast_io = true, }; static struct generic_pm_domain *imx_gpc_onecell_domains[] = { -- 2.20.1