From: Will Deacon <will@kernel.org>
To: Marc Zyngier <maz@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org,
kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Anshuman Khandual <anshuman.khandual@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>,
Doug Anderson <dianders@chromium.org>,
kernel-team@android.com
Subject: Re: [PATCH 3/8] arm64: cpufeature: Add CPU capability for AArch32 EL1 support
Date: Wed, 15 Apr 2020 18:00:29 +0100 [thread overview]
Message-ID: <20200415170029.GA19615@willie-the-truck> (raw)
In-Reply-To: <1b76993491176577567a0960a435dac0@kernel.org>
Hi Marc,
On Wed, Apr 15, 2020 at 09:55:57AM +0100, Marc Zyngier wrote:
> On 2020-04-14 22:31, Will Deacon wrote:
> > Although we emit a "SANITY CHECK" warning and taint the kernel if we
> > detect a CPU mismatch for AArch32 support at EL1, we still online the
> > CPU with disastrous consequences for any running 32-bit VMs.
> >
> > Introduce a capability for AArch32 support at EL1 so that late onlining
> > of incompatible CPUs is forbidden.
> >
> > Signed-off-by: Will Deacon <will@kernel.org>
>
> Definitely an improvement over the current situation, as the direct read
> of ID_AA64PFR0 was always a bit dodgy. Given that I'm pretty sure these new
> braindead SoCs are going to run an older version of the kernel, should we
> Cc stable for this?
I don't think there's a real need for -stable given that we do at least
taint the kernel. That's likely to annoy vendors enough to backport this
themselves ;)
Will
next prev parent reply other threads:[~2020-04-15 17:00 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-14 21:31 [PATCH 0/8] Relax sanity checking for mismatched AArch32 EL1 Will Deacon
2020-04-14 21:31 ` [PATCH 1/8] arm64: cpufeature: Relax check for IESB support Will Deacon
2020-04-15 10:02 ` Suzuki K Poulose
2020-04-14 21:31 ` [PATCH 2/8] arm64: cpufeature: Spell out register fields for ID_ISAR4 and ID_PFR1 Will Deacon
2020-04-15 10:09 ` Suzuki K Poulose
2020-04-14 21:31 ` [PATCH 3/8] arm64: cpufeature: Add CPU capability for AArch32 EL1 support Will Deacon
2020-04-15 8:55 ` Marc Zyngier
2020-04-15 17:00 ` Will Deacon [this message]
2020-04-15 10:13 ` Suzuki K Poulose
2020-04-15 10:14 ` Will Deacon
2020-04-15 13:15 ` Suzuki K Poulose
2020-04-15 13:22 ` Marc Zyngier
2020-04-17 9:44 ` Suzuki K Poulose
2020-04-14 21:31 ` [PATCH 4/8] arm64: cpufeature: Remove redundant call to id_aa64pfr0_32bit_el0() Will Deacon
2020-04-15 10:25 ` Suzuki K Poulose
2020-04-14 21:31 ` [PATCH 5/8] arm64: cpufeature: Factor out checking of AArch32 features Will Deacon
2020-04-15 10:36 ` Suzuki K Poulose
2020-04-14 21:31 ` [PATCH 6/8] arm64: cpufeature: Relax AArch32 system checks if EL1 is 64-bit only Will Deacon
2020-04-15 10:43 ` Suzuki K Poulose
2020-04-14 21:31 ` [PATCH 7/8] arm64: cpufeature: Relax checks for AArch32 support at EL[0-2] Will Deacon
2020-04-15 10:50 ` Suzuki K Poulose
2020-04-15 10:58 ` Will Deacon
2020-04-15 11:37 ` Suzuki K Poulose
2020-04-15 12:29 ` Will Deacon
2020-04-17 9:37 ` Suzuki K Poulose
2020-04-14 21:31 ` [PATCH 8/8] arm64: cpufeature: Add an overview comment for the cpufeature framework Will Deacon
2020-04-16 11:58 ` Will Deacon
2020-04-16 14:59 ` Suzuki K Poulose
2020-04-16 15:26 ` Marc Zyngier
2020-04-16 18:12 ` Will Deacon
2020-04-16 8:39 ` [PATCH 0/8] Relax sanity checking for mismatched AArch32 EL1 Sai Prakash Ranjan
2020-04-16 10:26 ` Sai Prakash Ranjan
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