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Peter Anvin" , Alex Deucher , Thomas Gleixner , Harry Wentland , mhiramat@kernel.org Subject: Re: AMD DC graphics display code enables -mhard-float, -msse, -msse2 without any visible FPU state protection Message-ID: <20200417202728.w2v3frkxqsgutb7h@outlook.office365.com> References: <4c5fe55d-9db9-2f61-59b2-1fb2e1b45ed0@amd.com> <20200402141308.GB20730@hirez.programming.kicks-ass.net> <20200409155956.GQ20760@hirez.programming.kicks-ass.net> <20200409170916.GR20760@hirez.programming.kicks-ass.net> <87a2f2fc-972d-ab9b-a29d-72f02d94e60e@amd.com> <20200409200125.GB2483@worktop.programming.kicks-ass.net> Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="y4kbkysvpam7ygts" Content-Disposition: inline In-Reply-To: <20200409200125.GB2483@worktop.programming.kicks-ass.net> X-ClientProxiedBy: BN6PR10CA0041.namprd10.prod.outlook.com (2603:10b6:404:109::27) To MW2PR12MB2524.namprd12.prod.outlook.com (2603:10b6:907:9::27) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from outlook.office365.com (2607:fea8:56a0:11a1::2) by BN6PR10CA0041.namprd10.prod.outlook.com (2603:10b6:404:109::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2921.25 via Frontend Transport; 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charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On 04/09, Peter Zijlstra wrote: > On Thu, Apr 09, 2020 at 08:15:57PM +0200, Christian K=F6nig wrote: > > Am 09.04.20 um 19:09 schrieb Peter Zijlstra: > > > On Thu, Apr 09, 2020 at 05:59:56PM +0200, Peter Zijlstra wrote: > > > [SNIP] > > > > I'll need another approach, let me consider. > > > Christian; it says these files are generated, does that generator know > > > which functions are wholly in FPU context and which are not? > >=20 > > Well that "generator" is still a human being :) > >=20 > > It's just that the formulae for the calculation come from the hardware = team > > and we are not able to easily transcript them to fixed point calculatio= ns. >=20 > Well, if it's a human, can this human respect the kernel coding style a > bit more :-) Some of that stuff is atrocious. >=20 > > > My current thinking is that if I annotate all functions that are whol= ly > > > inside kernel_fpu_start() with an __fpu function attribute, then I can > > > verify that any call from regular text to fpu text only happens inside > > > kernel_fpu_begin()/end(). And I can ensure that all !__fpu annotation > > > fuctions only contain !fpu instructions. > >=20 > > Yeah, that sounds like a good idea to me and should be easily doable. > >=20 > > > Can that generator add the __fpu function attribute or is that someth= ing > > > that would need to be done manually (which seems like it would be > > > painful, since it is quite a bit of code) ? > >=20 > > We are currently in the process of moving all the stuff which requires > > floating point into a single C file(s) and then make sure that we only = call > > those within kernel_fpu_begin()/end() blocks. >=20 > Can you make the build system stick all those .o files in a single > archive? That's the only way I can do call validation; external > relocatoin records do not contain the section. >=20 > > Annotating those function with __fpu or even saying to gcc that all cod= e of > > those files should go into a special text.fpu segment shouldn't be much= of a > > problem. >=20 > Guess what the __fpu attribute does ;-) >=20 > With the below patch (which is on to of newer versions of the objtool > patches send earlier, let me know if you want a full set) that only > converts a few files, but fully converts: >=20 > drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dcn_calcs.c >=20 > But building it (and this is an absolute pain; when you're reworking > this, can you pretty please also fix the Makefiles?), we get: Hi, I'm going to work on the FPU issues in the display code. In this sense, could you clarify a little bit more about the Makefile issues? Also, I applied the patch `[PATCH v4] x86: insn: Add insn_is_fpu()` and tried to reproduce the warning that you described but I didn't see it. Could you explain to me how I can check those warnings? Thanks > drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dcn_calcs.o: warning: ob= jtool: dcn_validate_bandwidth()+0x34fa: FPU instruction outside of kernel_f= pu_{begin,end}() >=20 > $ ./scripts/faddr2line defconfig-build/drivers/gpu/drm/amd/amdgpu/../disp= lay/dc/calcs/dcn_calcs.o dcn_validate_bandwidth+0x34fa > dcn_validate_bandwidth+0x34fa/0x57ce: > dcn_validate_bandwidth at /usr/src/linux-2.6/defconfig-build/../drivers/g= pu/drm/amd/amdgpu/../display/dc/calcs/dcn_calcs.c:1293 (discriminator 5) >=20 > # ./objdump-func.sh defconfig-build/drivers/gpu/drm/amd/amdgpu/../display= /dc/calcs/dcn_calcs.o dcn_validate_bandwidth | grep 34fa > 34fa 50fa: f2 0f 10 b5 60 ff ff movsd -0xa0(%rbp),%xmm6 >=20 > Which seems to indicate there's still problms with the current code. >=20 >=20 >=20 > --- > arch/x86/include/asm/fpu/api.h | 12 +++++++++++ > arch/x86/kernel/vmlinux.lds.S | 1 + > .../gpu/drm/amd/display/dc/calcs/dcn_calc_math.c | 25 +++++++++++-----= ------ > drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 4 ++-- > .../display/dc/dml/dcn20/display_rq_dlg_calc_20.c | 10 ++++----- > .../amd/display/dc/dml/display_rq_dlg_helpers.c | 2 +- > .../gpu/drm/amd/display/dc/dml/dml_common_defs.c | 2 +- > drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 2 +- > drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c | 10 ++++----- > drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c | 4 ++-- > drivers/gpu/drm/amd/display/dc/inc/dcn_calc_math.h | 2 ++ > tools/objtool/check.c | 7 +++++- > tools/objtool/elf.h | 2 +- > 13 files changed, 52 insertions(+), 31 deletions(-) >=20 > diff --git a/arch/x86/include/asm/fpu/api.h b/arch/x86/include/asm/fpu/ap= i.h > index 64be4426fda9..19eaf98bbb0a 100644 > --- a/arch/x86/include/asm/fpu/api.h > +++ b/arch/x86/include/asm/fpu/api.h > @@ -12,11 +12,23 @@ > #define _ASM_X86_FPU_API_H > #include >=20 > +#ifdef CONFIG_STACK_VALIDATION > + > +#define __fpu __section(".text.fpu") > + > #define _ASM_ANNOTATE_FPU(at) \ > ".pushsection .discard.fpu_safe\n" \ > ".long " #at " - .\n" \ > ".popsection\n" \ >=20 > +#else > + > +#define __fpu > + > +#define _ASM_ANNOTATE_FPU(at) > + > +#endif /* CONFIG_STACK_VALIDATION */ > + > #define annotate_fpu() ({ \ > asm volatile("%c0:\n\t" \ > _ASM_ANNOTATE_FPU(%c0b) \ > diff --git a/arch/x86/kernel/vmlinux.lds.S b/arch/x86/kernel/vmlinux.lds.S > index 1bf7e312361f..8442f8633d07 100644 > --- a/arch/x86/kernel/vmlinux.lds.S > +++ b/arch/x86/kernel/vmlinux.lds.S > @@ -139,6 +139,7 @@ SECTIONS > SOFTIRQENTRY_TEXT > *(.fixup) > *(.gnu.warning) > + *(.text.fpu) >=20 > #ifdef CONFIG_RETPOLINE > __indirect_thunk_start =3D .; > diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c b/drive= rs/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c > index 07d18e78de49..57ab3aafef5a 100644 > --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c > +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c > @@ -36,7 +36,7 @@ > * remain as-is as it provides us with a guarantee from HW that it is co= rrect. > */ >=20 > -float dcn_bw_mod(const float arg1, const float arg2) > +__fpu float dcn_bw_mod(const float arg1, const float arg2) > { > if (isNaN(arg1)) > return arg2; > @@ -45,7 +45,7 @@ float dcn_bw_mod(const float arg1, const float arg2) > return arg1 - arg1 * ((int) (arg1 / arg2)); > } >=20 > -float dcn_bw_min2(const float arg1, const float arg2) > +__fpu float dcn_bw_min2(const float arg1, const float arg2) > { > if (isNaN(arg1)) > return arg2; > @@ -58,7 +58,7 @@ unsigned int dcn_bw_max(const unsigned int arg1, const = unsigned int arg2) > { > return arg1 > arg2 ? arg1 : arg2; > } > -float dcn_bw_max2(const float arg1, const float arg2) > +__fpu float dcn_bw_max2(const float arg1, const float arg2) > { > if (isNaN(arg1)) > return arg2; > @@ -67,25 +67,26 @@ float dcn_bw_max2(const float arg1, const float arg2) > return arg1 > arg2 ? arg1 : arg2; > } >=20 > -float dcn_bw_floor2(const float arg, const float significance) > +__fpu float dcn_bw_floor2(const float arg, const float significance) > { > if (significance =3D=3D 0) > return 0; > return ((int) (arg / significance)) * significance; > } > -float dcn_bw_floor(const float arg) > + > +__fpu float dcn_bw_floor(const float arg) > { > return ((int) (arg)); > } >=20 > -float dcn_bw_ceil(const float arg) > +__fpu float dcn_bw_ceil(const float arg) > { > float flr =3D dcn_bw_floor2(arg, 1); >=20 > return flr + 0.00001 >=3D arg ? arg : flr + 1; > } >=20 > -float dcn_bw_ceil2(const float arg, const float significance) > +__fpu float dcn_bw_ceil2(const float arg, const float significance) > { > float flr =3D dcn_bw_floor2(arg, significance); > if (significance =3D=3D 0) > @@ -93,17 +94,17 @@ float dcn_bw_ceil2(const float arg, const float signi= ficance) > return flr + 0.00001 >=3D arg ? arg : flr + significance; > } >=20 > -float dcn_bw_max3(float v1, float v2, float v3) > +__fpu float dcn_bw_max3(float v1, float v2, float v3) > { > return v3 > dcn_bw_max2(v1, v2) ? v3 : dcn_bw_max2(v1, v2); > } >=20 > -float dcn_bw_max5(float v1, float v2, float v3, float v4, float v5) > +__fpu float dcn_bw_max5(float v1, float v2, float v3, float v4, float v5) > { > return dcn_bw_max3(v1, v2, v3) > dcn_bw_max2(v4, v5) ? dcn_bw_max3(v1, = v2, v3) : dcn_bw_max2(v4, v5); > } >=20 > -float dcn_bw_pow(float a, float exp) > +__fpu float dcn_bw_pow(float a, float exp) > { > float temp; > /*ASSERT(exp =3D=3D (int)exp);*/ > @@ -120,7 +121,7 @@ float dcn_bw_pow(float a, float exp) > } > } >=20 > -double dcn_bw_fabs(double a) > +__fpu double dcn_bw_fabs(double a) > { > if (a > 0) > return (a); > @@ -129,7 +130,7 @@ double dcn_bw_fabs(double a) > } >=20 >=20 > -float dcn_bw_log(float a, float b) > +__fpu float dcn_bw_log(float a, float b) > { > int * const exp_ptr =3D (int *)(&a); > int x =3D *exp_ptr; > diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/g= pu/drm/amd/display/dc/calcs/dcn_calcs.c > index 3960a8db94cb..b3e305d9d1c9 100644 > --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c > +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c > @@ -435,7 +435,7 @@ static void pipe_ctx_to_e2e_pipe_params ( >=20 > } >=20 > -static void dcn_bw_calc_rq_dlg_ttu( > +static __fpu void dcn_bw_calc_rq_dlg_ttu( > const struct dc *dc, > const struct dcn_bw_internal_vars *v, > struct pipe_ctx *pipe, > @@ -1388,7 +1388,7 @@ static unsigned int dcn_find_normalized_clock_vdd_L= evel( > return vdd_level; > } >=20 > -unsigned int dcn_find_dcfclk_suits_all( > +__fpu unsigned int dcn_find_dcfclk_suits_all( > const struct dc *dc, > struct dc_clocks *clocks) > { > diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc= _20.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c > index ca807846032f..0cbb58fc7fb8 100644 > --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c > +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c > @@ -115,7 +115,7 @@ static bool is_dual_plane(enum source_format_class so= urce_format) > return ret_val; > } >=20 > -static double get_refcyc_per_delivery(struct display_mode_lib *mode_lib, > +static __fpu double get_refcyc_per_delivery(struct display_mode_lib *mod= e_lib, > double refclk_freq_in_mhz, > double pclk_freq_in_mhz, > bool odm_combine, > @@ -162,7 +162,7 @@ static unsigned int get_blk_size_bytes(const enum sou= rce_macro_tile_size tile_si > return (4 * 1024); > } >=20 > -static void extract_rq_sizing_regs(struct display_mode_lib *mode_lib, > +static __fpu void extract_rq_sizing_regs(struct display_mode_lib *mode_l= ib, > display_data_rq_regs_st *rq_regs, > const display_data_rq_sizing_params_st rq_sizing) > { > @@ -313,7 +313,7 @@ static void handle_det_buf_split(struct display_mode_= lib *mode_lib, > full_swath_bytes_packed_c); > } >=20 > -static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib, > +static __fpu void get_meta_and_pte_attr(struct display_mode_lib *mode_li= b, > display_data_rq_dlg_params_st *rq_dlg_param, > display_data_rq_misc_params_st *rq_misc_param, > display_data_rq_sizing_params_st *rq_sizing_param, > @@ -763,7 +763,7 @@ void dml20_rq_dlg_get_rq_reg(struct display_mode_lib = *mode_lib, >=20 > // Note: currently taken in as is. > // Nice to decouple code from hw register implement and extract code tha= t are repeated for luma and chroma. > -static void dml20_rq_dlg_get_dlg_params(struct display_mode_lib *mode_li= b, > +static __fpu void dml20_rq_dlg_get_dlg_params(struct display_mode_lib *m= ode_lib, > const display_e2e_pipe_params_st *e2e_pipe_param, > const unsigned int num_pipes, > const unsigned int pipe_idx, > @@ -1611,7 +1611,7 @@ void dml20_rq_dlg_get_dlg_reg(struct display_mode_l= ib *mode_lib, > dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx); > } >=20 > -static void calculate_ttu_cursor(struct display_mode_lib *mode_lib, > +static __fpu void calculate_ttu_cursor(struct display_mode_lib *mode_lib, > double *refcyc_per_req_delivery_pre_cur, > double *refcyc_per_req_delivery_cur, > double refclk_freq_in_mhz, > diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c = b/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c > index e2d82aacd3bc..36541cba3894 100644 > --- a/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c > +++ b/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c > @@ -133,7 +133,7 @@ void print__rq_dlg_params_st(struct display_mode_lib = *mode_lib, display_rq_dlg_p > dml_print("DML_RQ_DLG_CALC: =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\n"); > } >=20 > -void print__dlg_sys_params_st(struct display_mode_lib *mode_lib, display= _dlg_sys_params_st dlg_sys_param) > +__fpu void print__dlg_sys_params_st(struct display_mode_lib *mode_lib, d= isplay_dlg_sys_params_st dlg_sys_param) > { > dml_print("DML_RQ_DLG_CALC: =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\n"); > dml_print("DML_RQ_DLG_CALC: DISPLAY_RQ_DLG_PARAM_ST\n"); > diff --git a/drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.c b/drive= rs/gpu/drm/amd/display/dc/dml/dml_common_defs.c > index 723af0b2dda0..e86b1d0128cf 100644 > --- a/drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.c > +++ b/drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.c > @@ -28,7 +28,7 @@ >=20 > #include "dml_inline_defs.h" >=20 > -double dml_round(double a) > +__fpu double dml_round(double a) > { > double round_pt =3D 0.5; > double ceil =3D dml_ceil(a, 1); > diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/dr= m/amd/display/dc/dsc/dc_dsc.c > index 87d682d25278..a0b0eb2f0fe3 100644 > --- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c > +++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c > @@ -323,7 +323,7 @@ static inline uint32_t calc_dsc_bpp_x16(uint32_t stre= am_bandwidth_kbps, uint32_t > /* Get DSC bandwidth range based on [min_bpp, max_bpp] target bitrate ra= nge, and timing's pixel clock > * and uncompressed bandwidth. > */ > -static void get_dsc_bandwidth_range( > +static __fpu void get_dsc_bandwidth_range( > const uint32_t min_bpp, > const uint32_t max_bpp, > const struct dsc_enc_caps *dsc_caps, > diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c b/drivers/gpu/d= rm/amd/display/dc/dsc/rc_calc.c > index 03ae15946c6d..535770930343 100644 > --- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c > +++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c > @@ -40,7 +40,7 @@ > break >=20 >=20 > -void get_qp_set(qp_set qps, enum colour_mode cm, enum bits_per_comp bpc,= enum max_min max_min, float bpp) > +__fpu void get_qp_set(qp_set qps, enum colour_mode cm, enum bits_per_com= p bpc, enum max_min max_min, float bpp) > { > int mode =3D MODE_SELECT(444, 422, 420); > int sel =3D table_hash(mode, bpc, max_min); > @@ -85,7 +85,7 @@ void get_qp_set(qp_set qps, enum colour_mode cm, enum b= its_per_comp bpc, enum ma > memcpy(qps, table[index].qps, sizeof(qp_set)); > } >=20 > -double dsc_roundf(double num) > +__fpu double dsc_roundf(double num) > { > if (num < 0.0) > num =3D num - 0.5; > @@ -95,7 +95,7 @@ double dsc_roundf(double num) > return (int)(num); > } >=20 > -double dsc_ceil(double num) > +__fpu double dsc_ceil(double num) > { > double retval =3D (int)num; >=20 > @@ -105,7 +105,7 @@ double dsc_ceil(double num) > return (int)retval; > } >=20 > -void get_ofs_set(qp_set ofs, enum colour_mode mode, float bpp) > +__fpu void get_ofs_set(qp_set ofs, enum colour_mode mode, float bpp) > { > int *p =3D ofs; >=20 > @@ -172,7 +172,7 @@ int median3(int a, int b, int c) > return b; > } >=20 > -void calc_rc_params(struct rc_params *rc, enum colour_mode cm, enum bits= _per_comp bpc, float bpp, int slice_width, int slice_height, int minor_vers= ion) > +__fpu void calc_rc_params(struct rc_params *rc, enum colour_mode cm, enu= m bits_per_comp bpc, float bpp, int slice_width, int slice_height, int mino= r_version) > { > float bpp_group; > float initial_xmit_delay_factor; > diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c b/drivers/g= pu/drm/amd/display/dc/dsc/rc_calc_dpi.c > index 1f6e63b71456..38b3c4ac96dd 100644 > --- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c > +++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c > @@ -98,7 +98,7 @@ static void copy_rc_to_cfg(struct drm_dsc_config *dsc_c= fg, const struct rc_param > dsc_cfg->rc_buf_thresh[i] =3D rc->rc_buf_thresh[i]; > } >=20 > -int dscc_compute_dsc_parameters(const struct drm_dsc_config *pps, struct= dsc_parameters *dsc_params) > +__fpu int dscc_compute_dsc_parameters(const struct drm_dsc_config *pps, = struct dsc_parameters *dsc_params) > { > enum colour_mode mode =3D pps->convert_rgb ? CM_RGB : > (pps->simple_422 ? CM_444 : > @@ -115,7 +115,7 @@ int dscc_compute_dsc_parameters(const struct drm_dsc_= config *pps, struct dsc_par >=20 > double d_bytes_per_pixel =3D dsc_ceil(bpp * slice_width / 8.0) / slice_= width; >=20 > - // TODO: Make sure the formula for calculating this is precise (ceiling= vs. floor, and at what point they should be applied) > + // TODO: Make sure the formula for calculating this is precise (ceiling= vs. floor, and at what point they should be applied > if (pps->native_422 || pps->native_420) > d_bytes_per_pixel /=3D 2; >=20 > diff --git a/drivers/gpu/drm/amd/display/dc/inc/dcn_calc_math.h b/drivers= /gpu/drm/amd/display/dc/inc/dcn_calc_math.h > index 45a07eeffbb6..d2ea6cf65f7e 100644 > --- a/drivers/gpu/drm/amd/display/dc/inc/dcn_calc_math.h > +++ b/drivers/gpu/drm/amd/display/dc/inc/dcn_calc_math.h > @@ -26,6 +26,8 @@ > #ifndef _DCN_CALC_MATH_H_ > #define _DCN_CALC_MATH_H_ >=20 > +#include > + > float dcn_bw_mod(const float arg1, const float arg2); > float dcn_bw_min2(const float arg1, const float arg2); > unsigned int dcn_bw_max(const unsigned int arg1, const unsigned int arg2= ); > diff --git a/tools/objtool/check.c b/tools/objtool/check.c > index 1607a698eccd..02a51fedd031 100644 > --- a/tools/objtool/check.c > +++ b/tools/objtool/check.c > @@ -252,6 +252,9 @@ static int decode_instructions(struct objtool_file *f= ile) > strncmp(sec->name, ".discard.", 9)) > sec->text =3D true; >=20 > + if (!strcmp(sec->name, ".text.fpu")) > + sec->fpu =3D true; > + > for (offset =3D 0; offset < sec->len; offset +=3D insn->len) { > insn =3D malloc(sizeof(*insn)); > if (!insn) { > @@ -288,8 +291,10 @@ static int decode_instructions(struct objtool_file *= file) > return -1; > } >=20 > - sym_for_each_insn(file, func, insn) > + sym_for_each_insn(file, func, insn) { > insn->func =3D func; > + insn->fpu_safe =3D sec->fpu; > + } > } > } >=20 > diff --git a/tools/objtool/elf.h b/tools/objtool/elf.h > index ebbb10c61e24..a743f2f28feb 100644 > --- a/tools/objtool/elf.h > +++ b/tools/objtool/elf.h > @@ -39,7 +39,7 @@ struct section { > char *name; > int idx; > unsigned int len; > - bool changed, text, rodata; > + bool changed, text, rodata, fpu; > }; >=20 > struct symbol { >=20 > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://nam11.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Flists= =2Efreedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=3D02%7C01%7CRodr= igo.Siqueira%40amd.com%7C8224db5fb3164b0f857c08d7dcc217d8%7C3dd8961fe4884e6= 08e11a82d994e183d%7C0%7C0%7C637220598535185983&sdata=3DZp4IQeEXy56dJhG3= 9TsIyvfC%2BYJYEoBuV%2Bna5VVvQpk%3D&reserved=3D0 --y4kbkysvpam7ygts Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEE4tZ+ii1mjMCMQbfkWJzP/comvP8FAl6aERUACgkQWJzP/com vP8pnRAApcGj0l25cQ+hO0hX4QIq3bNd1x6WLfViX+pD4chGtBbzCbORRHkXycfR UzDwRwAC9FZbWeLaDevc9O/Mt8C4LTt+XZfaiE56xRbEIvq/F9JizAiNwNCliq+y vtaGimR1lhFIUWG5pUdeBw9VosX9GzRlxOGnvntwH1kEVfgXlwkbC3qDQQzwH9LV mTQ64fcUWM9i5cZyLhyh4B4WsngfLcx+XghziO/6fqbeS31ufK7HI1mpm04nLwiq rvYF7K1I4WXKP9xtaFCkXzBqtH6So3kmatj2xxs+193d6BqDWq/t9gW6gXfH6AXS agpBOY+OTNAqK04E/nnfpd9il2WTxERJHoikTw2lTA6H6dFOpMdLp1DFzqlaXk3E t2EOn/EQTrXkNMDQUi0a0JfFN+fdNYpVSEtc3bbYnuKRImxMnoEciqI+GdeOmqsj 4+gh6gvl6K+kH2v2y+ICx72b1jRklSvZgZ2wTj1pIFraYrIoLdcAN7QeLdrxZ7uE 29O/i7Byv1RwJF4Ie6NfXDKQxt7C/uTjVzh7Pr3I6uLbFBqcg+dkE88z0qtTuotO EY1wAOYHddpJP42oz6emVBXDxfbcJNTzExbmVlGU+ETC1M0SSICIN1TovKSCYnXX j8iVIkY1BaQW9yr7dw6FjGUh7WW9MXoIsUl35G4WV9jwUcsA+x8= =xAE2 -----END PGP SIGNATURE----- --y4kbkysvpam7ygts--