From: Catalin Marinas <catalin.marinas@arm.com>
To: Russell King - ARM Linux admin <linux@armlinux.org.uk>
Cc: James Morse <james.morse@arm.com>,
Jonathan Cameron <Jonathan.Cameron@Huawei.com>,
info@metux.net, linux-kernel@vger.kernel.org,
linuxarm@huawei.com, allison@lohutok.net,
gregkh@linuxfoundation.org, Tian Tao <tiantao6@hisilicon.com>,
tglx@linutronix.de, Will Deacon <will@kernel.org>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH] arm32: fix flushcache syscall with device address
Date: Wed, 22 Apr 2020 14:56:43 +0100 [thread overview]
Message-ID: <20200422135642.GD3585@gaia> (raw)
In-Reply-To: <20200421165515.GF25745@shell.armlinux.org.uk>
On Tue, Apr 21, 2020 at 05:55:16PM +0100, Russell King wrote:
> On Tue, Apr 21, 2020 at 05:50:22PM +0100, James Morse wrote:
> > (Subject Nit: arm64, as that is what your patch modifies)
>
> That is irrelevent. This is a compatibility interface which is supposed
> to reflect the arm32 implementation. Augmenting a compatibility
> interface to do more than what it's counterpart that it's supposed to
> be compatible with is senseless.
>
> The API concerned is an ARM32 API which is expected to only be used
> for ensuring I/D cache coherency, it is not for DMA.
>
> Augmenting it on ARM64 for DMA is senseless.
I fully agree. I don't see any valid reason why this needs to be fixed.
It looks like some broken user process trying to do cache maintenance to
PoU on the mapped PCIe BAR (either inadvertently or for the wrong
reasons).
--
Catalin
next prev parent reply other threads:[~2020-04-22 13:56 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-21 8:08 [PATCH] arm32: fix flushcache syscall with device address Tian Tao
2020-04-21 8:12 ` Will Deacon
2020-04-21 11:16 ` Jonathan Cameron
2020-04-21 16:50 ` James Morse
2020-04-21 16:55 ` Russell King - ARM Linux admin
2020-04-22 13:56 ` Catalin Marinas [this message]
2020-04-21 12:22 ` Russell King - ARM Linux admin
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