From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1AAA7C55193 for ; Thu, 23 Apr 2020 20:36:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E157720781 for ; Thu, 23 Apr 2020 20:36:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=cerno.tech header.i=@cerno.tech header.b="Fn2d1x+/"; dkim=pass (2048-bit key) header.d=messagingengine.com header.i=@messagingengine.com header.b="X5O3GV4K" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726373AbgDWUgy (ORCPT ); Thu, 23 Apr 2020 16:36:54 -0400 Received: from new3-smtp.messagingengine.com ([66.111.4.229]:59747 "EHLO new3-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725877AbgDWUgx (ORCPT ); Thu, 23 Apr 2020 16:36:53 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailnew.nyi.internal (Postfix) with ESMTP id 4725158030B; Thu, 23 Apr 2020 16:36:49 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute4.internal (MEProxy); Thu, 23 Apr 2020 16:36:49 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cerno.tech; h= date:from:to:cc:subject:message-id:references:mime-version :content-type:in-reply-to; s=fm2; bh=Iubs+KISuHQ9VGeGg+cCp2xJSoU PuYVrphsLXiw5SFg=; b=Fn2d1x+/36iC3PGOTy5Cp2hHxpxTsbZXqEhCoWSU6fC Bh2uGjm8NzjGSIGOhUdI6jIFnaNlWlK/KNK0SO5YgDVKAzn9T8T4ClUJFkXWcI/L SrSHQwn+ywvkFIfMqeLT0tGOBnOJCf3GhECZDwsJXcOOkFJEZ5PO3Hg2TEHxt0Ji XXCiuCgBhfrNpF+Q4qgbmo0zisCBtKA1VkhzWKnI3UD+PuwtHOjrTI/5OtSrja0W 0xNGXCJ8ebZmLgh5iBcj0TUAG6xzsfP58vDHg4dtrP2Je050KddpO2V/+DEw4INi HTrBFJ8cS/EHw4cjf9yqCM3mqKMdTGT34HW7z+GoIEQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-proxy :x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s=fm2; bh=Iubs+K ISuHQ9VGeGg+cCp2xJSoUPuYVrphsLXiw5SFg=; b=X5O3GV4KFSkNBZXwi0gXe/ Az/rwjNsPXRiOZeR/DIobQrkLfux9vKSBPW2Q7Wch/uG7VG9fPmUEU8Kyi30iPJx 6rZFq866Z4AieJ/VQuUcLR0mV0pZLLxlv3ciLBDB/NhY/AvDjNVAvMjJxXjdCS6K u41z1fKpjs0erRbydhTf6J8lDzfZB7FSCFB8idsmUzAcZtLjWHuo6bbN3Dpzw+lv Xc1y1zz0vGYrNGmVPq0/4/8tCV+p/V1vxI12KqIjNELt9KhmHqpZLjuh1WSuMbeZ mWk/VcSn4C4MRsWk0RVAApy8MoL8ZK52EhiDYG9eBvoyLIChI6lqSRyqMDdlQG7g == X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgeduhedrgeelgdduudejucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhepfffhvffukfhfgggtuggjsehgtderredttddvnecuhfhrohhmpeforgigihhm vgcutfhiphgrrhguuceomhgrgihimhgvsegtvghrnhhordhtvggthheqnecukfhppeeltd drkeelrdeikedrjeeinecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghi lhhfrhhomhepmhgrgihimhgvsegtvghrnhhordhtvggthh X-ME-Proxy: Received: from localhost (lfbn-tou-1-1502-76.w90-89.abo.wanadoo.fr [90.89.68.76]) by mail.messagingengine.com (Postfix) with ESMTPA id CD893328005E; Thu, 23 Apr 2020 16:36:44 -0400 (EDT) Date: Thu, 23 Apr 2020 22:36:42 +0200 From: Maxime Ripard To: "H. Nikolaus Schaller" Cc: Neil Armstrong , Mark Rutland , Tony Lindgren , James Hogan , Jonathan Bakker , "open list:DRM PANEL DRIVERS" , linux-mips@vger.kernel.org, Paul Cercueil , linux-samsung-soc@vger.kernel.org, Discussions about the Letux Kernel , Paul Burton , Krzysztof Kozlowski , David Airlie , Chen-Yu Tsai , Kukjin Kim , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Daniel Vetter , Rob Herring , linux-omap , arm-soc , Thomas Bogendoerfer , Philipp Rossak , OpenPVRSGX Linux Driver Group , Linux Kernel Mailing List , Ralf Baechle , =?utf-8?Q?Beno=C3=AEt?= Cousson , kernel@pyra-handheld.com Subject: Re: [PATCH v6 00/12] ARM/MIPS: DTS: add child nodes describing the PVRSGX GPU present in some OMAP SoC and JZ4780 (and many more) Message-ID: <20200423203642.35ms4aarnv65tfp5@gilmour.lan> References: <20200421112129.zjmkmzo3aftksgka@gilmour.lan> <20200421141543.GU37466@atomide.com> <20200422065859.quy6ane5v7vsy5tf@gilmour.lan> <1AA57A0C-48E6-49BB-BB9A-2AAFFB371BCD@goldelico.com> <20200422151328.2oyqz7gqkbunmd6o@gilmour.lan> <07923B6C-4CCD-4B81-A98F-E19C43412A89@goldelico.com> <43688597-4b99-8f4d-9ad5-548ddff07f52@baylibre.com> <71F2F964-32C7-41E6-8F1A-A73161EA1BB3@goldelico.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="goo77pyirkr5psgn" Content-Disposition: inline In-Reply-To: <71F2F964-32C7-41E6-8F1A-A73161EA1BB3@goldelico.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --goo77pyirkr5psgn Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Apr 23, 2020 at 05:45:55PM +0200, H. Nikolaus Schaller wrote: > > Am 23.04.2020 um 17:00 schrieb Neil Armstrong : > >> One thing we can learn is that "core" seems to be a de facto standard= =20 > >> for the core clock-name. An alternative "gpu" is used by nvidia,gk20a.= txt. > >=20 > > Usually IPs needs a few clocks: > > - pclk or apb or reg: the clock clocking the "slave" bus to serve the r= egisters > > - axi or bus or ahb: the bus clocking the the "master" bus to get data = =66rom system memory > > - core: the actual clock feeding the GPU logic >=20 > And the sgx544 seems to have two such clocks. >=20 > > Sometimes you have a single clock for slave and master bus. > >=20 > > But you can also have separate clocks for shader cores, .. this depends= on the IP and it's architecture. > > The IP can also have memories with separate clocks, etc... >=20 > Indeed. >=20 > > But all these clocks can be source by an unique clock on a SoC, but dif= ferent on another > > SoC, this is why it's important to list them all, even optional. > >=20 > > You'll certainly have at least a reset signal, and a power domain, thes= e should exist and be optional. >=20 > Well, they exist only as hints in block diagrams of some SoC data > sheets (so we do not know if they represent the imagination > definitions) and the current driver code doesn't make use of it. Still > the gpu core works. >=20 > So I do not see any urgent need to add a complete list to the bindings > now. >=20 > Unless some special SoC integration makes use of them. Then it is IMHO > easier to extend the bindings by a follow-up patch than now thinking > about all potential options and bloating the bindings with things we > (the open source community) doesn't and can't know. >=20 > My goal is to keep the bindings as minimalistic as possible. And reset > lines and power domains are (at least for those we have in the works) > not needed to make working systems. >=20 > Therefore, for clocks I also would start with a minimalistic approach > for a single optional GPU core clock and leave out reset and power > completely. Like I said above, the DT is considered an ABI and you'll have to maintain backward compatibility (ie, newer kernel running with older DT). Therefore, you won't be able to require a new clock, reset or power-domain later on for example. I guess the question I'm really asking is: since you don't really know how the hardware is integrated at the moment, why should we have that discussion *now*. It's really not suprising that you don't know yet, so I'm not sure why we need to rush in the bindings. Maxime --goo77pyirkr5psgn Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXqH8WgAKCRDj7w1vZxhR xevnAQDosUT6nmUX0+zNQOj7IKsbVGpyycJhdLX1FoaJiEMTHgD/SWTr0aPp/w2C TCfnfiPupaeG8u9JV8QMCk/a58o6Xw8= =ygqv -----END PGP SIGNATURE----- --goo77pyirkr5psgn--