From: Anup Patel <anup.patel@wdc.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
Palmer Dabbelt <palmerdabbelt@google.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Paolo Bonzini <pbonzini@redhat.com>
Cc: Atish Patra <atish.patra@wdc.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Anup Patel <anup@brainfault.org>,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
Anup Patel <anup.patel@wdc.com>
Subject: [PATCH 3/3] RISC-V: Remove N-extension related defines
Date: Fri, 24 Apr 2020 10:29:28 +0530 [thread overview]
Message-ID: <20200424045928.79324-4-anup.patel@wdc.com> (raw)
In-Reply-To: <20200424045928.79324-1-anup.patel@wdc.com>
The RISC-V N-extension is still in draft state hence remove
N-extension related defines from asm/csr.h.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
arch/riscv/include/asm/csr.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 8e18d2c64399..cec462e198ce 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -51,13 +51,10 @@
#define CAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1))
/* Interrupt causes (minus the high bit) */
-#define IRQ_U_SOFT 0
#define IRQ_S_SOFT 1
#define IRQ_M_SOFT 3
-#define IRQ_U_TIMER 4
#define IRQ_S_TIMER 5
#define IRQ_M_TIMER 7
-#define IRQ_U_EXT 8
#define IRQ_S_EXT 9
#define IRQ_M_EXT 11
--
2.25.1
next prev parent reply other threads:[~2020-04-24 5:00 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-24 4:59 [PATCH 0/3] RISC-V KVM preparation Anup Patel
2020-04-24 4:59 ` [PATCH 1/3] RISC-V: Export riscv_cpuid_to_hartid_mask() API Anup Patel
2020-04-24 4:59 ` [PATCH 2/3] RISC-V: Add bitmap reprensenting ISA features common across CPUs Anup Patel
2020-04-24 4:59 ` Anup Patel [this message]
2020-05-04 20:01 ` [PATCH 0/3] RISC-V KVM preparation Palmer Dabbelt
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