From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2AD1DC83000 for ; Tue, 28 Apr 2020 20:58:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0E97E20B80 for ; Tue, 28 Apr 2020 20:58:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726522AbgD1U6U (ORCPT ); Tue, 28 Apr 2020 16:58:20 -0400 Received: from mga07.intel.com ([134.134.136.100]:12912 "EHLO mga07.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726274AbgD1U6T (ORCPT ); Tue, 28 Apr 2020 16:58:19 -0400 IronPort-SDR: scboWr2SMTqEtQK7Z5aZr8sCRYu8dg7hSOux9eAAY/7S1aGtaMrgHwKBXTst19sE/2qvjqa8sx VuYFerjZ/hwg== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Apr 2020 13:58:16 -0700 IronPort-SDR: pygPwoLUgJeiETJ1sloDS2DdGwuUtTzeCBhfufFSE3zoYrNEjecBG2eUJwiGcoh55mkFBtbLGR y3n+sZVRHBaw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,328,1583222400"; d="scan'208";a="367614156" Received: from romley-ivt3.sc.intel.com ([172.25.110.60]) by fmsmga001.fm.intel.com with ESMTP; 28 Apr 2020 13:58:16 -0700 Date: Tue, 28 Apr 2020 13:57:19 -0700 From: Fenghua Yu To: Thomas Gleixner Cc: Ingo Molnar , Borislav Petkov , H Peter Anvin , David Woodhouse , Lu Baolu , Dave Hansen , Tony Luck , Ashok Raj , Jacob Jun Pan , Dave Jiang , Sohil Mehta , Ravi V Shankar , linux-kernel , x86 , iommu@lists.linux-foundation.org Subject: Re: [PATCH 5/7] x86/mmu: Allocate/free PASID Message-ID: <20200428205718.GG242333@romley-ivt3.sc.intel.com> References: <1585596788-193989-1-git-send-email-fenghua.yu@intel.com> <1585596788-193989-6-git-send-email-fenghua.yu@intel.com> <87pnbus3du.fsf@nanos.tec.linutronix.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <87pnbus3du.fsf@nanos.tec.linutronix.de> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, Apr 26, 2020 at 04:55:25PM +0200, Thomas Gleixner wrote: > Fenghua Yu writes: > > diff --git a/arch/x86/include/asm/mmu.h b/arch/x86/include/asm/mmu.h > > index bdeae9291e5c..137bf51f19e6 100644 > > --- a/arch/x86/include/asm/mmu.h > > +++ b/arch/x86/include/asm/mmu.h > > @@ -50,6 +50,10 @@ typedef struct { > > u16 pkey_allocation_map; > > s16 execute_only_pkey; > > #endif > > + > > +#ifdef CONFIG_INTEL_IOMMU_SVM > > + int pasid; > > int? It's a value which gets programmed into the MSR along with the > valid bit (bit 31) set. BTW, ARM is working on PASID as well. Christoph suggested that the PASID should be defined in mm_struct instead of mm->context so that both ARM and X86 can access it: https://lore.kernel.org/linux-iommu/20200414170252.714402-1-jean-philippe@linaro.org/T/#mb57110ffe1aaa24750eeea4f93b611f0d1913911 So I will define "pasid" to mm_struct in a separate patch in the next version. Thanks. -Fenghua