From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
To: robh+dt@kernel.org, andrew@lunn.ch, f.fainelli@gmail.com,
linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org
Cc: jianxin.pan@amlogic.com, davem@davemloft.net,
netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Subject: [PATCH RFC v2 05/11] net: stmmac: dwmac-meson8b: Add the PRG_ETH0_ADJ_* bits
Date: Wed, 29 Apr 2020 22:16:38 +0200 [thread overview]
Message-ID: <20200429201644.1144546-6-martin.blumenstingl@googlemail.com> (raw)
In-Reply-To: <20200429201644.1144546-1-martin.blumenstingl@googlemail.com>
The PRG_ETH0_ADJ_* are used for applying the RGMII RX delay. The public
datasheets only have very limited description for these registers, but
Jianxin Pan provided more detailed documentation from an (unnamed)
Amlogic engineer. Add the PRG_ETH0_ADJ_* bits along with the improved
description.
Suggested-by: Jianxin Pan <jianxin.pan@amlogic.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
.../ethernet/stmicro/stmmac/dwmac-meson8b.c | 21 +++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
index 1d7526ee09dd..70075628c58e 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
@@ -48,6 +48,27 @@
#define PRG_ETH0_INVERTED_RMII_CLK BIT(11)
#define PRG_ETH0_TX_AND_PHY_REF_CLK BIT(12)
+/* Bypass (= 0, the signal from the GPIO input directly connects to the
+ * internal sampling) or enable (= 1) the internal logic for RXEN and RXD[3:0]
+ * timing tuning.
+ */
+#define PRG_ETH0_ADJ_ENABLE BIT(13)
+/* Controls whether the RXEN and RXD[3:0] signals should be aligned with the
+ * input RX rising/falling edge and sent to the Ethernet internals. This sets
+ * the automatically delay and skew automatically (internally).
+ */
+#define PRG_ETH0_ADJ_SETUP BIT(14)
+/* An internal counter based on the "timing-adjustment" clock. The counter is
+ * cleared on both, the falling and rising edge of the RX_CLK. This selects the
+ * delay (= the counter value) when to start sampling RXEN and RXD[3:0].
+ */
+#define PRG_ETH0_ADJ_DELAY GENMASK(19, 15)
+/* Adjusts the skew between each bit of RXEN and RXD[3:0]. If a signal has a
+ * large input delay, the bit for that signal (RXEN = bit 0, RXD[3] = bit 1,
+ * ...) can be configured to be 1 to compensate for a delay of about 1ns.
+ */
+#define PRG_ETH0_ADJ_SKEW GENMASK(24, 20)
+
#define MUX_CLK_NUM_PARENTS 2
struct meson8b_dwmac;
--
2.26.2
next prev parent reply other threads:[~2020-04-29 20:17 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-29 20:16 [PATCH RFC v2 00/11] dwmac-meson8b Ethernet RX delay configuration Martin Blumenstingl
2020-04-29 20:16 ` [PATCH RFC v2 01/11] dt-bindings: net: meson-dwmac: Add the amlogic,rx-delay-ns property Martin Blumenstingl
2020-05-01 15:26 ` Andrew Lunn
2020-05-12 14:51 ` Rob Herring
2020-04-29 20:16 ` [PATCH RFC v2 02/11] dt-bindings: net: dwmac-meson: Document the "timing-adjustment" clock Martin Blumenstingl
2020-05-01 15:27 ` Andrew Lunn
2020-05-01 21:09 ` Rob Herring
2020-05-01 21:53 ` Martin Blumenstingl
2020-05-10 22:34 ` Martin Blumenstingl
2020-04-29 20:16 ` [PATCH RFC v2 03/11] net: stmmac: dwmac-meson8b: use FIELD_PREP instead of open-coding it Martin Blumenstingl
2020-05-01 15:28 ` Andrew Lunn
2020-04-29 20:16 ` [PATCH RFC v2 04/11] net: stmmac: dwmac-meson8b: Move the documentation for the TX delay Martin Blumenstingl
2020-05-01 15:29 ` Andrew Lunn
2020-04-29 20:16 ` Martin Blumenstingl [this message]
2020-05-01 15:33 ` [PATCH RFC v2 05/11] net: stmmac: dwmac-meson8b: Add the PRG_ETH0_ADJ_* bits Andrew Lunn
2020-04-29 20:16 ` [PATCH RFC v2 06/11] net: stmmac: dwmac-meson8b: Fetch the "timing-adjustment" clock Martin Blumenstingl
2020-05-01 15:35 ` Andrew Lunn
2020-04-29 20:16 ` [PATCH RFC v2 07/11] net: stmmac: dwmac-meson8b: Make the clock enabling code re-usable Martin Blumenstingl
2020-05-01 15:37 ` Andrew Lunn
2020-04-29 20:16 ` [PATCH RFC v2 08/11] net: stmmac: dwmac-meson8b: add support for the RX delay configuration Martin Blumenstingl
2020-05-01 15:44 ` Andrew Lunn
2020-05-01 17:10 ` Martin Blumenstingl
2020-04-29 20:16 ` [PATCH DO NOT MERGE v2 09/11] arm64: dts: amlogic: Add the Ethernet "timing-adjustment" clock Martin Blumenstingl
2020-04-29 20:16 ` [PATCH DO NOT MERGE v2 10/11] ARM: dts: meson: " Martin Blumenstingl
2020-04-29 20:16 ` [PATCH DO NOT MERGE v2 11/11] ARM: dts: meson: Switch existing boards with RGMII PHY to "rgmii-id" Martin Blumenstingl
2020-04-29 21:29 ` [PATCH RFC v2 00/11] dwmac-meson8b Ethernet RX delay configuration Andrew Lunn
2020-05-01 14:49 ` Martin Blumenstingl
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