From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED0E7C47253 for ; Thu, 30 Apr 2020 19:01:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CDF9120836 for ; Thu, 30 Apr 2020 19:01:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="slgm+6f+" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726835AbgD3TBA (ORCPT ); Thu, 30 Apr 2020 15:01:00 -0400 Received: from rnd-relay.smtp.broadcom.com ([192.19.229.170]:56066 "EHLO rnd-relay.smtp.broadcom.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726346AbgD3TAx (ORCPT ); Thu, 30 Apr 2020 15:00:53 -0400 X-Greylist: delayed 317 seconds by postgrey-1.27 at vger.kernel.org; Thu, 30 Apr 2020 15:00:52 EDT Received: from mail-irv-17.broadcom.com (mail-irv-17.lvn.broadcom.net [10.75.242.48]) by rnd-relay.smtp.broadcom.com (Postfix) with ESMTP id 67CBD30C0C7; Thu, 30 Apr 2020 11:55:31 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.10.3 rnd-relay.smtp.broadcom.com 67CBD30C0C7 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1588272931; bh=CCuZ5sgSNCjCfw59P5WerFNtMeSC3recQoakjLMrWEA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=slgm+6f+5wLO+mcNnTAIGmgDbnnPEPI3PL5el1hU5F8aHaMkWZ3TpacglHsYToRrL oObmoc9tRxXM1KsN+X3xY2E5FrRsocrcVk0goZExKpdzv+aathwvujHmwDlFc0Eefh /vjhqv7ExtsSmDDiSjpXwT+dhqMk/QvUmXFM2RRM= Received: from stbsrv-and-01.and.broadcom.net (stbsrv-and-01.and.broadcom.net [10.28.16.211]) by mail-irv-17.broadcom.com (Postfix) with ESMTP id 0BF9E14008B; Thu, 30 Apr 2020 11:55:37 -0700 (PDT) From: Jim Quinlan To: james.quinlan@broadcom.com Cc: Jim Quinlan , Nicolas Saenz Julienne , Lorenzo Pieralisi , Rob Herring , Bjorn Helgaas , Florian Fainelli , bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE), linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-pci@vger.kernel.org (open list:PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 3/5] PCI: brcmstb: enable CRS Date: Thu, 30 Apr 2020 14:55:20 -0400 Message-Id: <20200430185522.4116-3-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200430185522.4116-1-james.quinlan@broadcom.com> References: <20200430185522.4116-1-james.quinlan@broadcom.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Jim Quinlan Configuration Retry Request Status is off by default on this PCIe controller. Turn it on. Signed-off-by: Jim Quinlan --- drivers/pci/controller/pcie-brcmstb.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index 5b0dec5971b8..2bc913c0262c 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -34,6 +34,9 @@ #define BRCM_PCIE_CAP_REGS 0x00ac /* Broadcom STB PCIe Register Offsets */ +#define PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL 0x00c8 +#define PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_EN_MASK 0x10 + #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188 #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc #define PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN 0x0 @@ -827,6 +830,12 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) pci_speed_string(pcie_link_speed[cls]), nlw, ssc_good ? "(SSC)" : "(!SSC)"); + /* Enable configuration request retry (CRS) */ + tmp = readl(base + PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL); + u32p_replace_bits(&tmp, 1, + PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_EN_MASK); + writel(tmp, base + PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL); + /* PCIe->SCB endian mode for BAR */ tmp = readl(base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1); u32p_replace_bits(&tmp, PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN, -- 2.17.1