From: Bjorn Helgaas <helgaas@kernel.org>
To: Jim Quinlan <james.quinlan@broadcom.com>
Cc: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Rob Herring <robh@kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>,
Florian Fainelli <f.fainelli@gmail.com>,
"maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE"
<bcm-kernel-feedback-list@broadcom.com>,
"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE"
<linux-rpi-kernel@lists.infradead.org>,
"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE"
<linux-arm-kernel@lists.infradead.org>,
"open list:PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS"
<linux-pci@vger.kernel.org>,
open list <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 5/5] PCI: brcmstb: disable L0s component of ASPM by default
Date: Thu, 30 Apr 2020 15:40:17 -0500 [thread overview]
Message-ID: <20200430204017.GA62947@bjorn-Precision-5520> (raw)
In-Reply-To: <20200430185522.4116-5-james.quinlan@broadcom.com>
On Thu, Apr 30, 2020 at 02:55:22PM -0400, Jim Quinlan wrote:
> From: Jim Quinlan <jquinlan@broadcom.com>
>
> Some informal internal experiments has shown that the BrcmSTB ASPM L0s
> savings may introduce an undesirable noise signal on some customers'
> boards. In addition, L0s was found lacking in realized power savings,
> especially relative to the L1 ASPM component. This is BrcmSTB's
> experience and may not hold for others. At any rate, we disable L0s
> savings by default unless the DT node has the 'brcm,aspm-en-l0s'
> property.
I assume this works by writing the PCIe Link Capabilities register,
which is read-only via the config space path used by the generic ASPM
code, so that code thinks the device doesn't support L0s at all.
Documentation/devicetree/bindings/pci/rockchip-pcie-host.txt includes
an "aspm-no-l0s" property. It'd be nice if this could use the same
property.
> Signed-off-by: Jim Quinlan <jquinlan@broadcom.com>
> ---
> drivers/pci/controller/pcie-brcmstb.c | 14 +++++++++++++-
> 1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
> index 2bc913c0262c..bc1d514b19e4 100644
> --- a/drivers/pci/controller/pcie-brcmstb.c
> +++ b/drivers/pci/controller/pcie-brcmstb.c
> @@ -44,6 +44,9 @@
> #define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
> #define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
>
> +#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY 0x04dc
> +#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK 0xc00
> +
> #define PCIE_RC_DL_MDIO_ADDR 0x1100
> #define PCIE_RC_DL_MDIO_WR_DATA 0x1104
> #define PCIE_RC_DL_MDIO_RD_DATA 0x1108
> @@ -696,7 +699,7 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
> int num_out_wins = 0;
> u16 nlw, cls, lnksta;
> int i, ret;
> - u32 tmp;
> + u32 tmp, aspm_support;
>
> /* Reset the bridge */
> brcm_pcie_bridge_sw_init_set(pcie, 1);
> @@ -806,6 +809,15 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
> num_out_wins++;
> }
>
> + /* Only support ASPM L1 unless L0s is explicitly desired */
> + aspm_support = PCIE_LINK_STATE_L1;
> + if (of_property_read_bool(pcie->np, "brcm,aspm-en-l0s"))
> + aspm_support |= PCIE_LINK_STATE_L0S;
> + tmp = readl(base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
> + u32p_replace_bits(&tmp, aspm_support,
> + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK);
> + writel(tmp, base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
> +
> /*
> * For config space accesses on the RC, show the right class for
> * a PCIe-PCIe bridge (the default setting is to be EP mode).
> --
> 2.17.1
>
next prev parent reply other threads:[~2020-04-30 20:40 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-30 18:55 [PATCH 1/5] PCI: brcmstb: don't clk_put() a managed clock Jim Quinlan
2020-04-30 18:55 ` [PATCH 2/5] PCI: brcmstb: fix window register offset from 4 to 8 Jim Quinlan
2020-04-30 19:07 ` Florian Fainelli
2020-04-30 20:43 ` Bjorn Helgaas
2020-04-30 18:55 ` [PATCH 3/5] PCI: brcmstb: enable CRS Jim Quinlan
2020-04-30 19:19 ` Florian Fainelli
2020-04-30 20:32 ` Bjorn Helgaas
2020-04-30 21:00 ` Jim Quinlan
2020-04-30 18:55 ` [PATCH 4/5] dt-bindings: PCI: brcmstb: New prop 'brcm,aspm-en-l0s' Jim Quinlan
2020-04-30 19:20 ` Florian Fainelli
2020-04-30 18:55 ` [PATCH 5/5] PCI: brcmstb: disable L0s component of ASPM by default Jim Quinlan
2020-04-30 19:21 ` Florian Fainelli
2020-04-30 20:40 ` Bjorn Helgaas [this message]
2020-04-30 21:17 ` Jim Quinlan
2020-04-30 19:05 ` [PATCH 1/5] PCI: brcmstb: don't clk_put() a managed clock Florian Fainelli
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