From: Thomas Gleixner <tglx@linutronix.de>
To: LKML <linux-kernel@vger.kernel.org>
Cc: x86@kernel.org, "Paul E. McKenney" <paulmck@kernel.org>,
Andy Lutomirski <luto@kernel.org>,
Alexandre Chartre <alexandre.chartre@oracle.com>,
Frederic Weisbecker <frederic@kernel.org>,
Paolo Bonzini <pbonzini@redhat.com>,
Sean Christopherson <sean.j.christopherson@intel.com>,
Masami Hiramatsu <mhiramat@kernel.org>,
Petr Mladek <pmladek@suse.com>,
Steven Rostedt <rostedt@goodmis.org>,
Joel Fernandes <joel@joelfernandes.org>,
Boris Ostrovsky <boris.ostrovsky@oracle.com>,
Juergen Gross <jgross@suse.com>, Brian Gerst <brgerst@gmail.com>,
Mathieu Desnoyers <mathieu.desnoyers@efficios.com>,
Josh Poimboeuf <jpoimboe@redhat.com>,
Will Deacon <will@kernel.org>,
Peter Zijlstra <peterz@infradead.org>
Subject: [patch V4 part 4 15/24] x86/db: Split out dr6/7 handling
Date: Tue, 05 May 2020 15:49:41 +0200 [thread overview]
Message-ID: <20200505135314.808628211@linutronix.de> (raw)
In-Reply-To: 20200505134926.578885807@linutronix.de
From: Peter Zijlstra <peterz@infradead.org>
DR6/7 should be handled before nmi_enter() is invoked and restore after
nmi_exit() to minimize the exposure.
Split it out into helper inlines and bring it into the correct order.
Signed-off-by: Peter Zijlstra <peterz@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
arch/x86/kernel/hw_breakpoint.c | 6 ---
arch/x86/kernel/traps.c | 62 +++++++++++++++++++++++++++-------------
2 files changed, 44 insertions(+), 24 deletions(-)
--- a/arch/x86/kernel/hw_breakpoint.c
+++ b/arch/x86/kernel/hw_breakpoint.c
@@ -464,7 +464,7 @@ static int hw_breakpoint_handler(struct
{
int i, cpu, rc = NOTIFY_STOP;
struct perf_event *bp;
- unsigned long dr7, dr6;
+ unsigned long dr6;
unsigned long *dr6_p;
/* The DR6 value is pointed by args->err */
@@ -479,9 +479,6 @@ static int hw_breakpoint_handler(struct
if ((dr6 & DR_TRAP_BITS) == 0)
return NOTIFY_DONE;
- get_debugreg(dr7, 7);
- /* Disable breakpoints during exception handling */
- set_debugreg(0UL, 7);
/*
* Assert that local interrupts are disabled
* Reset the DRn bits in the virtualized register value.
@@ -538,7 +535,6 @@ static int hw_breakpoint_handler(struct
(dr6 & (~DR_TRAP_BITS)))
rc = NOTIFY_DONE;
- set_debugreg(dr7, 7);
put_cpu();
return rc;
--- a/arch/x86/kernel/traps.c
+++ b/arch/x86/kernel/traps.c
@@ -691,6 +691,44 @@ static bool is_sysenter_singlestep(struc
#endif
}
+static __always_inline void debug_enter(unsigned long *dr6, unsigned long *dr7)
+{
+ /*
+ * Disable breakpoints during exception handling; recursive exceptions
+ * are exceedingly 'fun'.
+ *
+ * Since this function is NOKPROBE, and that also applies to
+ * HW_BREAKPOINT_X, we can't hit a breakpoint before this (XXX except a
+ * HW_BREAKPOINT_W on our stack)
+ *
+ * Entry text is excluded for HW_BP_X and cpu_entry_area, which
+ * includes the entry stack is excluded for everything.
+ */
+ get_debugreg(*dr7, 6);
+ set_debugreg(0, 7);
+
+ /*
+ * The Intel SDM says:
+ *
+ * Certain debug exceptions may clear bits 0-3. The remaining
+ * contents of the DR6 register are never cleared by the
+ * processor. To avoid confusion in identifying debug
+ * exceptions, debug handlers should clear the register before
+ * returning to the interrupted task.
+ *
+ * Keep it simple: clear DR6 immediately.
+ */
+ get_debugreg(*dr6, 6);
+ set_debugreg(0, 6);
+ /* Filter out all the reserved bits which are preset to 1 */
+ *dr6 &= ~DR6_RESERVED;
+}
+
+static __always_inline void debug_exit(unsigned long dr7)
+{
+ set_debugreg(dr7, 7);
+}
+
/*
* Our handling of the processor debug registers is non-trivial.
* We do not clear them on entry and exit from the kernel. Therefore
@@ -718,28 +756,13 @@ static bool is_sysenter_singlestep(struc
dotraplinkage void do_debug(struct pt_regs *regs, long error_code)
{
struct task_struct *tsk = current;
+ unsigned long dr6, dr7;
int user_icebp = 0;
- unsigned long dr6;
int si_code;
- nmi_enter();
-
- get_debugreg(dr6, 6);
- /*
- * The Intel SDM says:
- *
- * Certain debug exceptions may clear bits 0-3. The remaining
- * contents of the DR6 register are never cleared by the
- * processor. To avoid confusion in identifying debug
- * exceptions, debug handlers should clear the register before
- * returning to the interrupted task.
- *
- * Keep it simple: clear DR6 immediately.
- */
- set_debugreg(0, 6);
+ debug_enter(&dr6, &dr7);
- /* Filter out all the reserved bits which are preset to 1 */
- dr6 &= ~DR6_RESERVED;
+ nmi_enter();
/*
* The SDM says "The processor clears the BTF flag when it
@@ -777,7 +800,7 @@ dotraplinkage void do_debug(struct pt_re
#endif
if (notify_die(DIE_DEBUG, "debug", regs, (long)&dr6, error_code,
- SIGTRAP) == NOTIFY_STOP)
+ SIGTRAP) == NOTIFY_STOP)
goto exit;
/*
@@ -816,6 +839,7 @@ dotraplinkage void do_debug(struct pt_re
exit:
nmi_exit();
+ debug_exit(dr7);
}
NOKPROBE_SYMBOL(do_debug);
next prev parent reply other threads:[~2020-05-05 14:19 UTC|newest]
Thread overview: 94+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-05 13:49 [patch V4 part 4 00/24] x86/entry: Entry/exception code rework, nasty exceptions Thomas Gleixner
2020-05-05 13:49 ` [patch V4 part 4 01/24] x86/int3: Ensure that poke_int3_handler() is not traced Thomas Gleixner
2020-05-14 4:57 ` Andy Lutomirski
2020-05-19 19:58 ` [tip: x86/entry] " tip-bot2 for Thomas Gleixner
2020-05-05 13:49 ` [patch V4 part 4 02/24] x86/int3: Avoid atomic instrumentation Thomas Gleixner
2020-05-08 13:27 ` Masami Hiramatsu
2020-05-14 4:57 ` Andy Lutomirski
2020-05-14 9:32 ` Peter Zijlstra
2020-05-14 12:51 ` Thomas Gleixner
2020-05-14 13:15 ` Peter Zijlstra
2020-05-14 14:55 ` Andy Lutomirski
2020-05-14 15:06 ` Thomas Gleixner
2020-05-14 15:08 ` Andy Lutomirski
2020-05-14 15:10 ` Peter Zijlstra
2020-05-19 19:58 ` [tip: x86/entry] " tip-bot2 for Peter Zijlstra
2020-05-05 13:49 ` [patch V4 part 4 03/24] lib/bsearch: Provide __always_inline variant Thomas Gleixner
2020-05-14 4:58 ` Andy Lutomirski
2020-05-19 19:58 ` [tip: x86/entry] " tip-bot2 for Peter Zijlstra
2020-05-05 13:49 ` [patch V4 part 4 04/24] x86/int3: Inline bsearch() Thomas Gleixner
2020-05-14 4:58 ` Andy Lutomirski
2020-05-19 19:58 ` [tip: x86/entry] " tip-bot2 for Peter Zijlstra
2020-05-05 13:49 ` [patch V4 part 4 05/24] x86/entry: Provide IDTENTRY_RAW Thomas Gleixner
2020-05-14 4:59 ` Andy Lutomirski
2020-05-19 19:58 ` [tip: x86/entry] x86/idtentry: " tip-bot2 for Thomas Gleixner
2020-05-05 13:49 ` [patch V4 part 4 06/24] x86/entry: Convert INT3 exception to IDTENTRY_RAW Thomas Gleixner
2020-05-14 5:01 ` Andy Lutomirski
2020-05-19 19:58 ` [tip: x86/entry] " tip-bot2 for Thomas Gleixner
2020-05-05 13:49 ` [patch V4 part 4 07/24] x86/traps: Split int3 handler up Thomas Gleixner
2020-05-14 5:03 ` Andy Lutomirski
2020-05-14 9:39 ` Peter Zijlstra
2020-05-19 19:58 ` [tip: x86/entry] " tip-bot2 for Peter Zijlstra
2020-05-05 13:49 ` [patch V4 part 4 08/24] x86/entry: Provide IDTENTRY_IST Thomas Gleixner
2020-05-14 16:39 ` Andy Lutomirski
2020-05-14 18:44 ` Thomas Gleixner
2020-05-19 19:58 ` [tip: x86/entry] x86/idtentry: " tip-bot2 for Thomas Gleixner
2020-05-05 13:49 ` [patch V4 part 4 09/24] x86/mce: Move nmi_enter/exit() into the entry point Thomas Gleixner
2020-05-15 5:23 ` Andy Lutomirski
2020-05-19 19:58 ` [tip: x86/entry] " tip-bot2 for Thomas Gleixner
2020-05-05 13:49 ` [patch V4 part 4 10/24] x86/entry: Convert Machine Check to IDTENTRY_IST Thomas Gleixner
2020-05-15 5:24 ` Andy Lutomirski
2020-05-19 19:58 ` [tip: x86/entry] " tip-bot2 for Thomas Gleixner
2020-05-05 13:49 ` [patch V4 part 4 11/24] x86/mce: Use untraced rd/wrmsr in the MCE offline/crash check Thomas Gleixner
2020-05-15 5:24 ` Andy Lutomirski
2020-05-19 19:58 ` [tip: x86/entry] " tip-bot2 for Thomas Gleixner
2020-05-05 13:49 ` [patch V4 part 4 12/24] x86/idtentry: Provide IDTENTRY_XEN for XEN/PV Thomas Gleixner
2020-05-15 5:25 ` Andy Lutomirski
2020-05-19 19:58 ` [tip: x86/entry] " tip-bot2 for Thomas Gleixner
2020-05-05 13:49 ` [patch V4 part 4 13/24] x86/entry: Convert NMI to IDTENTRY_NMI Thomas Gleixner
2020-05-15 5:26 ` Andy Lutomirski
2020-05-19 19:58 ` [tip: x86/entry] " tip-bot2 for Thomas Gleixner
2020-05-05 13:49 ` [patch V4 part 4 14/24] x86/nmi: Protect NMI entry against instrumentation Thomas Gleixner
2020-05-15 5:26 ` Andy Lutomirski
2020-05-19 19:58 ` [tip: x86/entry] " tip-bot2 for Thomas Gleixner
2020-05-05 13:49 ` Thomas Gleixner [this message]
2020-05-07 17:18 ` [patch V4 part 4 15/24] x86/db: Split out dr6/7 handling Alexandre Chartre
2020-05-08 8:59 ` Peter Zijlstra
2020-05-08 11:58 ` Thomas Gleixner
2020-05-08 12:45 ` Peter Zijlstra
2020-05-14 2:24 ` Mathieu Desnoyers
2020-05-14 17:28 ` Thomas Gleixner
2020-05-14 17:46 ` Mathieu Desnoyers
2020-05-15 14:32 ` Thomas Gleixner
2020-05-14 18:06 ` Steven Rostedt
2020-05-15 5:37 ` Andy Lutomirski
2020-05-19 19:58 ` [tip: x86/entry] " tip-bot2 for Peter Zijlstra
2020-05-05 13:49 ` [patch V4 part 4 16/24] x86/entry: Convert Debug exception to IDTENTRY_DB Thomas Gleixner
2020-05-15 5:27 ` Andy Lutomirski
2020-05-19 19:58 ` [tip: x86/entry] " tip-bot2 for Thomas Gleixner
2020-05-05 13:49 ` [patch V4 part 4 17/24] x86/entry/64: Remove error code clearing from #DB and #MCE ASM stub Thomas Gleixner
2020-05-15 5:27 ` Andy Lutomirski
2020-05-19 19:58 ` [tip: x86/entry] " tip-bot2 for Thomas Gleixner
2020-05-05 13:49 ` [patch V4 part 4 18/24] x86/entry: Provide IDTRENTRY_NOIST variants for #DB and #MC Thomas Gleixner
2020-05-15 5:29 ` Andy Lutomirski
2020-05-19 19:58 ` [tip: x86/entry] x86/idtentry: " tip-bot2 for Thomas Gleixner
2020-05-05 13:49 ` [patch V4 part 4 19/24] x86/entry: Implement user mode C entry points for #DB and #MCE Thomas Gleixner
2020-05-15 5:32 ` Andy Lutomirski
2020-05-19 19:58 ` [tip: x86/entry] " tip-bot2 for Thomas Gleixner
2020-05-05 13:49 ` [patch V4 part 4 20/24] x86/traps: Restructure #DB handling Thomas Gleixner
2020-05-15 5:39 ` Andy Lutomirski
2020-05-19 19:58 ` [tip: x86/entry] " tip-bot2 for Thomas Gleixner
2020-05-05 13:49 ` [patch V4 part 4 21/24] x86/traps: Address objtool noinstr complaints in #DB Thomas Gleixner
2020-05-15 5:39 ` Andy Lutomirski
2020-05-19 19:58 ` [tip: x86/entry] " tip-bot2 for Thomas Gleixner
2020-05-05 13:49 ` [patch V4 part 4 22/24] x86/mce: Address objtools noinstr complaints Thomas Gleixner
2020-05-15 5:40 ` Andy Lutomirski
2020-05-19 19:58 ` [tip: x86/entry] " tip-bot2 for Thomas Gleixner
2020-05-05 13:49 ` [patch V4 part 4 23/24] x86/entry: Provide IDTENTRY_DF Thomas Gleixner
2020-05-15 5:41 ` Andy Lutomirski
2020-05-15 15:01 ` Thomas Gleixner
2020-05-19 19:58 ` [tip: x86/entry] x86/idtentry: " tip-bot2 for Thomas Gleixner
2020-05-19 19:58 ` [tip: x86/entry] x86/entry: Convert double fault exception to IDTENTRY_DF tip-bot2 for Thomas Gleixner
2020-05-05 13:49 ` [patch V4 part 4 24/24] " Thomas Gleixner
2020-05-07 19:55 ` Alexandre Chartre
2020-05-15 5:42 ` Andy Lutomirski
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