From: <Sergey.Semin@baikalelectronics.ru>
To: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Serge Semin <Sergey.Semin@baikalelectronics.ru>,
Serge Semin <fancer.lancer@gmail.com>,
Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>,
Paul Burton <paulburton@kernel.org>,
Ralf Baechle <ralf@linux-mips.org>, Arnd Bergmann <arnd@arndb.de>,
Rob Herring <robh+dt@kernel.org>, <linux-pm@vger.kernel.org>,
<devicetree@vger.kernel.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Thomas Gleixner <tglx@linutronix.de>,
Allison Randal <allison@lohutok.net>,
<linux-mips@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH v2 17/20] mips: Add udelay lpj numbers adjustment
Date: Wed, 6 May 2020 20:42:35 +0300 [thread overview]
Message-ID: <20200506174238.15385-18-Sergey.Semin@baikalelectronics.ru> (raw)
In-Reply-To: <20200506174238.15385-1-Sergey.Semin@baikalelectronics.ru>
From: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Loops-per-jiffies is a special number which represents a number of
noop-loop cycles per CPU-scheduler quantum - jiffies. As you
understand aside from CPU-specific implementation it depends on
the CPU frequency. So when a platform has the CPU frequency fixed,
we have no problem and the current udelay interface will work
just fine. But as soon as CPU-freq driver is enabled and the cores
frequency changes, we'll end up with distorted udelay's. In order
to fix this we have to accordinly adjust the per-CPU udelay_val
(the same as the global loops_per_jiffy) number. This can be done
in the CPU-freq transition event handler. We subscribe to that event
in the MIPS arch time-inititalization method.
Co-developed-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Signed-off-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-pm@vger.kernel.org
Cc: devicetree@vger.kernel.org
---
arch/mips/kernel/time.c | 70 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 70 insertions(+)
diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c
index 37e9413a393d..ce89e18af024 100644
--- a/arch/mips/kernel/time.c
+++ b/arch/mips/kernel/time.c
@@ -18,12 +18,82 @@
#include <linux/smp.h>
#include <linux/spinlock.h>
#include <linux/export.h>
+#include <linux/cpufreq.h>
+#include <linux/delay.h>
#include <asm/cpu-features.h>
#include <asm/cpu-type.h>
#include <asm/div64.h>
#include <asm/time.h>
+#ifdef CONFIG_CPU_FREQ
+
+static DEFINE_PER_CPU(unsigned long, pcp_lpj_ref);
+static DEFINE_PER_CPU(unsigned long, pcp_lpj_ref_freq);
+static unsigned long glb_lpj_ref;
+static unsigned long glb_lpj_ref_freq;
+
+static int cpufreq_callback(struct notifier_block *nb,
+ unsigned long val, void *data)
+{
+ struct cpufreq_freqs *freq = data;
+ struct cpumask *cpus = freq->policy->cpus;
+ unsigned long lpj;
+ int cpu;
+
+ /*
+ * Skip lpj numbers adjustment if the CPU-freq transition is safe for
+ * the loops delay. (Is this possible?)
+ */
+ if (freq->flags & CPUFREQ_CONST_LOOPS)
+ return NOTIFY_OK;
+
+ /* Save the initial values of the lpjes for future scaling. */
+ if (!glb_lpj_ref) {
+ glb_lpj_ref = boot_cpu_data.udelay_val;
+ glb_lpj_ref_freq = freq->old;
+
+ for_each_online_cpu(cpu) {
+ per_cpu(pcp_lpj_ref, cpu) =
+ cpu_data[cpu].udelay_val;
+ per_cpu(pcp_lpj_ref_freq, cpu) = freq->old;
+ }
+ }
+
+ /*
+ * Adjust global lpj variable and per-CPU udelay_val number in
+ * accordance with the new CPU frequency.
+ */
+ if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
+ (val == CPUFREQ_POSTCHANGE && freq->old > freq->new)) {
+ loops_per_jiffy = cpufreq_scale(glb_lpj_ref,
+ glb_lpj_ref_freq,
+ freq->new);
+
+ for_each_cpu(cpu, cpus) {
+ lpj = cpufreq_scale(per_cpu(pcp_lpj_ref, cpu),
+ per_cpu(pcp_lpj_ref_freq, cpu),
+ freq->new);
+ cpu_data[cpu].udelay_val = (unsigned int)lpj;
+ }
+ }
+
+ return NOTIFY_OK;
+}
+
+static struct notifier_block cpufreq_notifier = {
+ .notifier_call = cpufreq_callback,
+};
+
+static int __init register_cpufreq_notifier(void)
+{
+ return cpufreq_register_notifier(&cpufreq_notifier,
+ CPUFREQ_TRANSITION_NOTIFIER);
+}
+core_initcall(register_cpufreq_notifier);
+
+#endif /* !CONFIG_CPU_FREQ */
+
/*
* forward reference
*/
--
2.25.1
next prev parent reply other threads:[~2020-05-06 17:44 UTC|newest]
Thread overview: 89+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-06 12:46 [PATCH 00/22] mips: Prepare MIPS-arch code for Baikal-T1 SoC support Sergey.Semin
2020-05-06 17:42 ` [PATCH v2 00/20] " Sergey.Semin
2020-05-06 17:42 ` [PATCH v2 01/20] dt-bindings: power: Convert mti,mips-cpc to DT schema Sergey.Semin
2020-05-14 15:09 ` Rob Herring
2020-05-14 18:04 ` Serge Semin
2020-05-06 17:42 ` [PATCH v2 02/20] dt-bindings: bus: Add MIPS CDMM controller Sergey.Semin
2020-05-14 15:09 ` Rob Herring
2020-05-14 18:05 ` Serge Semin
2020-05-06 17:42 ` [PATCH v2 03/20] dt-bindings: Add vendor prefix for Baikal Electronics, JSC Sergey.Semin
2020-05-06 17:55 ` Sam Ravnborg
2020-05-06 19:20 ` Serge Semin
2020-05-06 19:26 ` Sam Ravnborg
2020-05-06 20:18 ` Serge Semin
2020-05-14 18:13 ` Serge Semin
2020-05-14 18:31 ` Rob Herring
2020-05-06 17:42 ` [PATCH v2 04/20] mips: cm: Fix an invalid error code of INTVN_*_ERR Sergey.Semin
2020-05-07 11:10 ` Thomas Bogendoerfer
2020-05-07 21:32 ` Serge Semin
2020-05-06 17:42 ` [PATCH v2 05/20] mips: cm: Add L2 ECC/parity errors reporting Sergey.Semin
2020-05-07 11:17 ` Thomas Bogendoerfer
2020-05-07 21:38 ` Serge Semin
2020-05-06 17:42 ` [PATCH v2 06/20] mips: Add MIPS32 Release 5 support Sergey.Semin
2020-05-08 13:30 ` Thomas Bogendoerfer
2020-05-10 22:05 ` Serge Semin
2020-05-06 17:42 ` [PATCH v2 07/20] mips: Add MIPS Warrior P5600 support Sergey.Semin
2020-05-07 11:17 ` Thomas Bogendoerfer
2020-05-07 21:19 ` Serge Semin
2020-05-08 9:32 ` Thomas Bogendoerfer
2020-05-08 12:21 ` Thomas Bogendoerfer
2020-05-10 22:09 ` Serge Semin
2020-05-06 17:42 ` [PATCH v2 08/20] mips: Fix cpu_has_mips64r1/2 activation for MIPS32 CPUs Sergey.Semin
2020-05-08 13:28 ` Thomas Bogendoerfer
2020-05-10 23:59 ` Serge Semin
2020-05-06 17:42 ` [PATCH v2 09/20] mips: Add CP0 Write Merge config support Sergey.Semin
2020-05-06 17:42 ` [PATCH v2 10/20] mips: Add CONFIG/CONFIG6/Cause reg fields macro Sergey.Semin
2020-05-06 17:42 ` [PATCH v2 11/20] mips: MAAR: Use more precise address mask Sergey.Semin
2020-05-07 11:09 ` Thomas Bogendoerfer
2020-05-07 19:13 ` Serge Semin
2020-05-08 9:22 ` Thomas Bogendoerfer
2020-05-10 22:13 ` Serge Semin
2020-05-06 17:42 ` [PATCH v2 12/20] mips: MAAR: Add XPA mode support Sergey.Semin
2020-05-19 15:42 ` Thomas Bogendoerfer
2020-05-20 11:30 ` Serge Semin
2020-05-06 17:42 ` [PATCH v2 13/20] mips: early_printk_8250: Use offset-sized IO-mem accessors Sergey.Semin
2020-05-06 17:42 ` [PATCH v2 14/20] mips: Use offset-sized IO-mem accessors in CPS debug printout Sergey.Semin
2020-05-06 18:16 ` Sergei Shtylyov
2020-05-06 19:52 ` Serge Semin
2020-05-06 17:42 ` [PATCH v2 15/20] mips: cdmm: Add mti,mips-cdmm dtb node support Sergey.Semin
2020-05-06 17:42 ` [PATCH v2 16/20] bus: cdmm: Add MIPS R5 arch support Sergey.Semin
2020-05-06 17:42 ` Sergey.Semin [this message]
2020-05-08 12:15 ` [PATCH v2 17/20] mips: Add udelay lpj numbers adjustment Jiaxun Yang
2020-05-06 17:42 ` [PATCH v2 18/20] mips: csrc-r4k: Decrease r4k-clocksource rating if CPU_FREQ enabled Sergey.Semin
2020-05-08 15:41 ` Thomas Bogendoerfer
2020-05-11 13:31 ` Serge Semin
2020-05-15 7:48 ` Serge Semin
2020-05-15 21:06 ` Thomas Bogendoerfer
2020-05-16 11:55 ` Serge Semin
2020-05-18 13:48 ` Serge Semin
2020-05-18 16:32 ` Thomas Bogendoerfer
2020-05-18 20:57 ` Serge Semin
2020-05-19 15:50 ` Thomas Bogendoerfer
2020-05-20 11:59 ` Serge Semin
2020-05-20 14:03 ` Serge Semin
2020-05-20 18:40 ` Thomas Bogendoerfer
2020-05-20 21:13 ` Serge Semin
2020-05-20 12:12 ` Serge Semin
2020-05-20 12:21 ` Serge Semin
2020-05-20 13:38 ` Thomas Bogendoerfer
2020-05-20 13:48 ` Serge Semin
2020-05-20 18:30 ` Thomas Bogendoerfer
2020-05-20 21:12 ` Serge Semin
2020-05-06 17:42 ` [PATCH v2 19/20] mips: cevt-r4k: Update the r4k-clockevent frequency in sync with CPU Sergey.Semin
2020-05-08 15:40 ` Thomas Bogendoerfer
2020-05-11 0:34 ` Serge Semin
2020-05-06 17:42 ` [PATCH v2 20/20] cpufreq: Return zero on success in boost sw setting Sergey.Semin
2020-05-15 15:58 ` Rafael J. Wysocki
2020-05-16 12:52 ` Serge Semin
2020-05-18 7:41 ` Viresh Kumar
2020-05-18 9:53 ` Rafael J. Wysocki
2020-05-18 10:11 ` Viresh Kumar
2020-05-18 10:22 ` Rafael J. Wysocki
2020-05-18 10:24 ` Viresh Kumar
2020-05-18 10:31 ` Serge Semin
2020-05-18 10:41 ` Rafael J. Wysocki
2020-05-18 10:46 ` Serge Semin
2020-05-18 10:51 ` Rafael J. Wysocki
2020-05-18 10:56 ` Serge Semin
2020-05-18 11:05 ` Rafael J. Wysocki
2020-05-19 1:50 ` Xiongfeng Wang
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