From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E36B7C54E49 for ; Thu, 7 May 2020 18:29:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CAB90208DB for ; Thu, 7 May 2020 18:29:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727092AbgEGS3L (ORCPT ); Thu, 7 May 2020 14:29:11 -0400 Received: from mga17.intel.com ([192.55.52.151]:25470 "EHLO mga17.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726320AbgEGS3L (ORCPT ); Thu, 7 May 2020 14:29:11 -0400 IronPort-SDR: ci8xYIijSYUjNrgjD8jz5lU5qf0vx/R0ftZUm48wNOnaFk07VcWZmnqhAFNuFp9XWGl9bxM/5B UM4bUT6FC+xA== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 May 2020 11:29:10 -0700 IronPort-SDR: wMCF1cDvnibopdXFyBYMTMWQUgrGoVywPKBnfFBshtu66Lml/9Uhcx1CeU2Dk+bYh/7TpE83ne 9LAth0IHca1A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,364,1583222400"; d="scan'208";a="296619233" Received: from smile.fi.intel.com (HELO smile) ([10.237.68.40]) by orsmga008.jf.intel.com with ESMTP; 07 May 2020 11:29:03 -0700 Received: from andy by smile with local (Exim 4.93) (envelope-from ) id 1jWlGc-005H6v-15; Thu, 07 May 2020 21:29:06 +0300 Date: Thu, 7 May 2020 21:29:06 +0300 From: Andy Shevchenko To: Serge Semin Cc: Thomas Bogendoerfer , Greg Kroah-Hartman , Jiri Slaby , Serge Semin , Alexey Malahov , Maxim Kaurkin , Pavel Parkhomenko , Alexey Kolotnikov , Ramil Zaripov , Ekaterina Skachko , Vadim Vlasov , Paul Burton , Ralf Baechle , Arnd Bergmann , Long Cheng , Maxime Ripard , Catalin Marinas , Will Deacon , Russell King , linux-mips@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 0/4] serial: 8250_dw: Fix ref clock usage Message-ID: <20200507182906.GC185537@smile.fi.intel.com> References: <20200323024611.16039-1-Sergey.Semin@baikalelectronics.ru> <20200506233136.11842-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200506233136.11842-1-Sergey.Semin@baikalelectronics.ru> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, May 07, 2020 at 02:31:31AM +0300, Serge Semin wrote: > It might be dangerous if an UART port reference clock rate is suddenly > changed. In particular the 8250 port drivers (and AFAICS most of the tty > drivers using common clock framework clocks) rely either on the > exclusive reference clock utilization or on the ref clock rate being > always constant. Needless to say that it turns out not true and if some > other service suddenly changes the clock rate behind an UART port driver > back it's no good. So the port might not only end up with an invalid > uartclk value saved, but may also experience a distorted output/input > data since such action will effectively update the programmed baud-clock. > We discovered such problem on Baikal-T1 SoC where two DW 8250 ports have > got a shared reference clock. Allwinner SoC is equipped with an UART, > which clock is derived from the CPU PLL clock source, so the CPU frequency > change might be propagated down up to the serial port reference clock. > This patchset provides a way to fix the problem to the 8250 serial port > controllers and mostly fixes it for the DW 8250-compatible UART. I say > mostly because due to not having a facility to pause/stop and resume/ > restart on-going transfers we implemented the UART clock rate update > procedure executed post factum of the actual reference clock rate change. > > In addition the patchset includes a few fixes we discovered when were > working the issue. First one concerns the maximum baud rate setting used > to determine a serial port baud based on the current UART port clock rate. > Another one simplifies the ref clock rate setting procedure a bit. > > This patchset is rebased and tested on the mainline Linux kernel 5.7-rc4: > 0e698dfa2822 ("Linux 5.7-rc4") > tag: v5.7-rc4 Thanks! I will look at them later, but first impression that the first approach narrowed to the certain SoC (by matching compatible string) looks better solution for time being. > Changelog v3: > - Refactor the original patch to adjust the UART port divisor instead of > requesting an exclusive ref clock utilization. > > Signed-off-by: Serge Semin > Cc: Alexey Malahov > Cc: Maxim Kaurkin > Cc: Pavel Parkhomenko > Cc: Alexey Kolotnikov > Cc: Ramil Zaripov > Cc: Ekaterina Skachko > Cc: Vadim Vlasov > Cc: Alexey Kolotnikov > Cc: Paul Burton > Cc: Ralf Baechle > Cc: Arnd Bergmann > Cc: Long Cheng > Cc: Andy Shevchenko > Cc: Maxime Ripard > Cc: Catalin Marinas > Cc: Will Deacon > Cc: Russell King > Cc: linux-mips@vger.kernel.org > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-mediatek@lists.infradead.org > Cc: linux-serial@vger.kernel.org > Cc: linux-kernel@vger.kernel.org > > Serge Semin (4): > serial: 8250: Fix max baud limit in generic 8250 port > serial: 8250: Add 8250 port clock update method > serial: 8250_dw: Simplify the ref clock rate setting procedure > serial: 8250_dw: Fix common clocks usage race condition > > drivers/tty/serial/8250/8250_dw.c | 125 +++++++++++++++++++++++++--- > drivers/tty/serial/8250/8250_port.c | 42 +++++++++- > include/linux/serial_8250.h | 2 + > 3 files changed, 156 insertions(+), 13 deletions(-) > > -- > 2.25.1 > -- With Best Regards, Andy Shevchenko