From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 174F8C38A2A for ; Thu, 7 May 2020 20:16:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E86A0208CA for ; Thu, 7 May 2020 20:16:03 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="HqaoCa1W" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728547AbgEGUQD (ORCPT ); Thu, 7 May 2020 16:16:03 -0400 Received: from rnd-relay.smtp.broadcom.com ([192.19.229.170]:47470 "EHLO rnd-relay.smtp.broadcom.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726320AbgEGUQB (ORCPT ); Thu, 7 May 2020 16:16:01 -0400 Received: from mail-irv-17.broadcom.com (mail-irv-17.lvn.broadcom.net [10.75.242.48]) by rnd-relay.smtp.broadcom.com (Postfix) with ESMTP id AAB2130C018; Thu, 7 May 2020 13:15:23 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.10.3 rnd-relay.smtp.broadcom.com AAB2130C018 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1588882523; bh=AlMuEa61meXpiw5wjlL0cyiH8vZu7sD/qJXFoQ+Bns4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HqaoCa1WX8ZST6ZZ+BgC7wfj5/9nEKpmI4k/g9O/x0KUC32AGa5zim6ZCXLFsHyEK 5dKicYKrrY7TWhYIG2AOA3/4FCiV5xBz69bNsuZcvdLauQZinqTuNTt3vq5YDREgdw ios/0Epm7ucTMtZLt0dOuxDSH9XvpGrc11JKnbL8= Received: from stbsrv-and-01.and.broadcom.net (stbsrv-and-01.and.broadcom.net [10.28.16.211]) by mail-irv-17.broadcom.com (Postfix) with ESMTP id 9CB7C14008C; Thu, 7 May 2020 13:15:57 -0700 (PDT) From: Jim Quinlan To: james.quinlan@broadcom.com Cc: Jim Quinlan , Nicolas Saenz Julienne , Lorenzo Pieralisi , Rob Herring , Bjorn Helgaas , Florian Fainelli , bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE), Andrew Murray , Jeremy Linton , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-pci@vger.kernel.org (open list:PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3 2/4] PCI: brcmstb: Fix window register offset from 4 to 8 Date: Thu, 7 May 2020 16:15:41 -0400 Message-Id: <20200507201544.43432-3-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200507201544.43432-1-james.quinlan@broadcom.com> References: <20200507201544.43432-1-james.quinlan@broadcom.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Jim Quinlan The outbound memory window registers were being referenced with an incorrect stride offset. This probably wasn't noticed previously as there was likely only one such window employed. Signed-off-by: Jim Quinlan Acked-by: Florian Fainelli Acked-by: Nicolas Saenz Julienne Fixes: c0452137034b ("PCI: brcmstb: Add Broadcom STB PCIe host controller driver") --- drivers/pci/controller/pcie-brcmstb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index 454917ee9241..5b0dec5971b8 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -54,11 +54,11 @@ #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c #define PCIE_MEM_WIN0_LO(win) \ - PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 4) + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 8) #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010 #define PCIE_MEM_WIN0_HI(win) \ - PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 4) + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 8) #define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c #define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f -- 2.17.1