From: Sasha Levin <sashal@kernel.org>
To: linux-kernel@vger.kernel.org, tglx@linutronix.de, bp@alien8.de,
luto@kernel.org
Cc: hpa@zytor.com, dave.hansen@intel.com, tony.luck@intel.com,
ak@linux.intel.com, ravi.v.shankar@intel.com,
chang.seok.bae@intel.com, Sasha Levin <sashal@kernel.org>,
Vegard Nossum <vegard.nossum@oracle.com>
Subject: [PATCH v12 06/18] x86/entry/64: Introduce the FIND_PERCPU_BASE macro
Date: Mon, 11 May 2020 00:52:59 -0400 [thread overview]
Message-ID: <20200511045311.4785-7-sashal@kernel.org> (raw)
In-Reply-To: <20200511045311.4785-1-sashal@kernel.org>
From: "Chang S. Bae" <chang.seok.bae@intel.com>
GS base is used to find per-CPU data in the kernel. But when GS base is
unknown, the per-CPU base can be found from the per_cpu_offset table with a
CPU NR. The CPU NR is extracted from the limit field of the CPUNODE entry
in GDT, or by the RDPID instruction. This is a prerequisite for using
FSGSBASE in the low level entry code.
Also, add the GAS-compatible RDPID macro as binutils 2.21 does not support
it. Support is added in version 2.27.
Suggested-by: H. Peter Anvin <hpa@zytor.com>
Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Reviewed-by: Tony Luck <tony.luck@intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Dave Hansen <dave.hansen@intel.com>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Vegard Nossum <vegard.nossum@oracle.com>
---
arch/x86/entry/calling.h | 34 ++++++++++++++++++++++++++++++++++
arch/x86/include/asm/inst.h | 15 +++++++++++++++
2 files changed, 49 insertions(+)
diff --git a/arch/x86/entry/calling.h b/arch/x86/entry/calling.h
index 1c7f13bb67286..29982fe140541 100644
--- a/arch/x86/entry/calling.h
+++ b/arch/x86/entry/calling.h
@@ -6,6 +6,7 @@
#include <asm/percpu.h>
#include <asm/asm-offsets.h>
#include <asm/processor-flags.h>
+#include <asm/inst.h>
/*
@@ -349,6 +350,39 @@ For 32-bit we have the following conventions - kernel is built with
#endif
.endm
+#ifdef CONFIG_SMP
+
+/*
+ * CPU/node NR is loaded from the limit (size) field of a special segment
+ * descriptor entry in GDT.
+ */
+.macro LOAD_CPU_AND_NODE_SEG_LIMIT reg:req
+ movq $__CPUNODE_SEG, \reg
+ lsl \reg, \reg
+.endm
+
+/*
+ * Fetch the per-CPU GS base value for this processor and put it in @reg.
+ * We normally use %gs for accessing per-CPU data, but we are setting up
+ * %gs here and obviously can not use %gs itself to access per-CPU data.
+ */
+.macro GET_PERCPU_BASE reg:req
+ ALTERNATIVE \
+ "LOAD_CPU_AND_NODE_SEG_LIMIT \reg", \
+ "RDPID \reg", \
+ X86_FEATURE_RDPID
+ andq $VDSO_CPUNODE_MASK, \reg
+ movq __per_cpu_offset(, \reg, 8), \reg
+.endm
+
+#else
+
+.macro GET_PERCPU_BASE reg:req
+ movq pcpu_unit_offsets(%rip), \reg
+.endm
+
+#endif /* CONFIG_SMP */
+
/*
* This does 'call enter_from_user_mode' unless we can avoid it based on
* kernel config or using the static jump infrastructure.
diff --git a/arch/x86/include/asm/inst.h b/arch/x86/include/asm/inst.h
index f5a796da07f88..d063841a17e39 100644
--- a/arch/x86/include/asm/inst.h
+++ b/arch/x86/include/asm/inst.h
@@ -306,6 +306,21 @@
.endif
MODRM 0xc0 movq_r64_xmm_opd1 movq_r64_xmm_opd2
.endm
+
+.macro RDPID opd
+ REG_TYPE rdpid_opd_type \opd
+ .if rdpid_opd_type == REG_TYPE_R64
+ R64_NUM rdpid_opd \opd
+ .else
+ R32_NUM rdpid_opd \opd
+ .endif
+ .byte 0xf3
+ .if rdpid_opd > 7
+ PFX_REX rdpid_opd 0
+ .endif
+ .byte 0x0f, 0xc7
+ MODRM 0xc0 rdpid_opd 0x7
+.endm
#endif
#endif
--
2.20.1
next prev parent reply other threads:[~2020-05-11 4:54 UTC|newest]
Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-11 4:52 [PATCH v12 00/18] Enable FSGSBASE instructions Sasha Levin
2020-05-11 4:52 ` [PATCH v12 01/18] x86/ptrace: Prevent ptrace from clearing the FS/GS selector Sasha Levin
2020-05-11 4:52 ` [PATCH v12 02/18] selftests/x86/fsgsbase: Test GS selector on ptracer-induced GS base write Sasha Levin
2020-05-11 4:52 ` [PATCH v12 03/18] x86/cpu: Add 'unsafe_fsgsbase' to enable CR4.FSGSBASE Sasha Levin
2020-05-11 4:52 ` [PATCH v12 04/18] x86/entry/64: Clean up paranoid exit Sasha Levin
2020-05-11 4:52 ` [PATCH v12 05/18] x86/entry/64: Switch CR3 before SWAPGS in paranoid entry Sasha Levin
2020-05-11 4:52 ` Sasha Levin [this message]
2020-05-11 4:53 ` [PATCH v12 07/18] x86/entry/64: Handle FSGSBASE enabled paranoid entry/exit Sasha Levin
2020-05-11 4:53 ` [PATCH v12 08/18] x86/entry/64: Document GSBASE handling in the paranoid path Sasha Levin
2020-05-11 4:53 ` [PATCH v12 09/18] x86/fsgsbase/64: Add intrinsics for FSGSBASE instructions Sasha Levin
2020-05-11 4:53 ` [PATCH v12 10/18] x86/fsgsbase/64: Enable FSGSBASE instructions in helper functions Sasha Levin
2020-05-18 18:20 ` Thomas Gleixner
2020-05-18 20:24 ` Sasha Levin
2020-05-18 22:59 ` Thomas Gleixner
2020-05-19 12:20 ` David Laight
2020-05-19 14:48 ` Thomas Gleixner
2020-05-20 9:13 ` David Laight
2020-05-11 4:53 ` [PATCH v12 11/18] x86/fsgsbase/64: Use FSGSBASE in switch_to() if available Sasha Levin
2020-05-11 4:53 ` [PATCH v12 12/18] x86/fsgsbase/64: move save_fsgs to header file Sasha Levin
2020-05-11 4:53 ` [PATCH v12 13/18] x86/fsgsbase/64: Use FSGSBASE instructions on thread copy and ptrace Sasha Levin
2020-05-11 4:53 ` [PATCH v12 14/18] x86/speculation/swapgs: Check FSGSBASE in enabling SWAPGS mitigation Sasha Levin
2020-05-11 4:53 ` [PATCH v12 15/18] selftests/x86/fsgsbase: Test ptracer-induced GS base write with FSGSBASE Sasha Levin
2020-05-11 4:53 ` [PATCH v12 16/18] x86/fsgsbase/64: Enable FSGSBASE on 64bit by default and add a chicken bit Sasha Levin
2020-05-11 4:53 ` [PATCH v12 17/18] x86/elf: Enumerate kernel FSGSBASE capability in AT_HWCAP2 Sasha Levin
2020-05-11 4:53 ` [PATCH v12 18/18] Documentation/x86/64: Add documentation for GS/FS addressing mode Sasha Levin
2020-05-15 9:24 ` [PATCH v12 00/18] Enable FSGSBASE instructions Jarkko Sakkinen
2020-05-15 16:40 ` Sasha Levin
2020-05-15 17:55 ` Andi Kleen
2020-05-15 23:07 ` Sasha Levin
2020-05-16 12:21 ` Jarkko Sakkinen
2020-05-16 9:50 ` Jarkko Sakkinen
2020-05-18 15:34 ` Andi Kleen
2020-05-18 20:01 ` Jarkko Sakkinen
2020-05-18 23:03 ` Thomas Gleixner
2020-05-19 16:48 ` Jarkko Sakkinen
2020-05-22 20:14 ` Don Porter
2020-05-22 20:55 ` Dave Hansen
2020-05-23 0:45 ` Thomas Gleixner
2020-05-24 19:45 ` hpa
2020-05-24 21:19 ` Sasha Levin
2020-05-24 23:44 ` hpa
2020-05-25 7:54 ` Richard Weinberger
2020-05-25 21:56 ` Tony Luck
2020-05-26 8:12 ` David Laight
2020-05-26 8:23 ` Richard Weinberger
2020-05-27 8:31 ` Jarkko Sakkinen
2020-05-26 12:42 ` Don Porter
2020-05-26 20:27 ` Sasha Levin
2020-05-26 22:03 ` Don Porter
2020-05-26 22:51 ` Sasha Levin
2020-05-28 17:37 ` Don Porter
2020-05-28 10:29 ` Thomas Gleixner
2020-05-28 17:40 ` Don Porter
2020-05-28 18:38 ` Andy Lutomirski
2020-05-29 15:27 ` Wojtek Porczyk
2020-06-25 15:27 ` Don Porter
2020-06-25 21:37 ` Jarkko Sakkinen
2020-07-18 18:19 ` Don Porter
2020-07-23 3:23 ` Jarkko Sakkinen
2020-05-28 19:19 ` Jarkko Sakkinen
2020-05-28 19:41 ` Sasha Levin
2020-05-29 3:07 ` Jarkko Sakkinen
2020-05-29 3:10 ` Jarkko Sakkinen
2020-06-25 15:30 ` Don Porter
2020-06-25 21:40 ` Jarkko Sakkinen
2020-05-23 4:19 ` Andi Kleen
2020-05-28 10:36 ` Thomas Gleixner
2020-05-27 8:20 ` Jarkko Sakkinen
2020-05-27 12:42 ` Wojtek Porczyk
2020-05-18 9:51 ` Thomas Gleixner
2020-05-18 15:16 ` Sasha Levin
2020-05-18 18:28 ` Thomas Gleixner
2020-05-18 19:36 ` Jarkko Sakkinen
2020-05-18 6:18 ` Christoph Hellwig
2020-05-18 12:33 ` Sasha Levin
2020-05-18 14:53 ` Thomas Gleixner
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