From: Rob Herring <robh@kernel.org>
To: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: linux-amlogic@lists.infradead.org, ulf.hansson@linaro.org,
linux-mmc@vger.kernel.org, jbrunet@baylibre.com,
robh+dt@kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, yinxin_1989@aliyun.com,
lnykww@gmail.com, jianxin.pan@amlogic.com,
linux-arm-kernel@lists.infradead.org, linux.amoon@gmail.com
Subject: Re: [PATCH v7 1/2] dt-bindings: mmc: Document the Amlogic Meson SDHC MMC host controller
Date: Tue, 12 May 2020 17:44:17 -0500 [thread overview]
Message-ID: <20200512224417.GA11220@bogus> (raw)
In-Reply-To: <20200512204147.504087-2-martin.blumenstingl@googlemail.com>
On Tue, 12 May 2020 22:41:46 +0200, Martin Blumenstingl wrote:
> This documents the devicetree bindings for the SDHC MMC host controller
> found in Meson6, Meson8, Meson8b and Meson8m2 SoCs. It can use a
> bus-width of 1/4/8-bit and it supports eMMC spec 4.4x/4.5x including
> HS200 mode (up to 100MHz clock). It embeds an internal clock controller
> which outputs four clocks (mod_clk, sd_clk, tx_clk and rx_clk) and is
> fed by four external input clocks (clkin[0-3]). "pclk" is the module
> register clock, it has to be enabled to access the registers.
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
> .../bindings/mmc/amlogic,meson-mx-sdhc.yaml | 68 +++++++++++++++++++
> 1 file changed, 68 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdhc.yaml
>
Reviewed-by: Rob Herring <robh@kernel.org>
next prev parent reply other threads:[~2020-05-12 22:44 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-12 20:41 [PATCH v7 0/2] Amlogic 32-bit Meson SoC SDHC MMC controller driver Martin Blumenstingl
2020-05-12 20:41 ` [PATCH v7 1/2] dt-bindings: mmc: Document the Amlogic Meson SDHC MMC host controller Martin Blumenstingl
2020-05-12 22:44 ` Rob Herring [this message]
2020-05-12 20:41 ` [PATCH v7 2/2] mmc: host: meson-mx-sdhc: new driver for the Amlogic Meson SDHC host Martin Blumenstingl
2020-05-13 12:04 ` Ulf Hansson
2020-05-13 12:40 ` Jerome Brunet
2020-05-15 7:09 ` [PATCH v7 0/2] Amlogic 32-bit Meson SoC SDHC MMC controller driver Ulf Hansson
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