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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id o17sm237457otp.79.2020.05.14.19.50.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 May 2020 19:50:48 -0700 (PDT) Received: (nullmailer pid 30844 invoked by uid 1000); Fri, 15 May 2020 02:50:47 -0000 Date: Thu, 14 May 2020 21:50:47 -0500 From: Rob Herring To: Sarthak Garg Cc: adrian.hunter@intel.com, ulf.hansson@linaro.org, vbadigan@codeaurora.org, stummala@codeaurora.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" Subject: Re: [PATCH V1 1/7] dt-bindings: mmc: Add information for DLL register properties Message-ID: <20200515025047.GA27895@bogus> References: <1588838535-6050-1-git-send-email-sartgarg@codeaurora.org> <1588838535-6050-2-git-send-email-sartgarg@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1588838535-6050-2-git-send-email-sartgarg@codeaurora.org> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, May 07, 2020 at 01:32:08PM +0530, Sarthak Garg wrote: > Add information regarding DLL register properties for getting target > specific configurations. These DLL register settings may vary from > target to target. > > Also new compatible string value for sm8250 target. > > Signed-off-by: Sarthak Garg > --- > Documentation/devicetree/bindings/mmc/sdhci-msm.txt | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt > index 5445931..b8e1d2b 100644 > --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt > +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt > @@ -17,6 +17,7 @@ Required properties: > "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4" > "qcom,msm8992-sdhci", "qcom,sdhci-msm-v4" > "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4" > + "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5" > "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5" > "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5" > "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; > @@ -46,6 +47,13 @@ Required properties: > "cal" - reference clock for RCLK delay calibration (optional) > "sleep" - sleep clock for RCLK delay calibration (optional) > > +- qcom,ddr-config: Certain chipsets and platforms require particular settings > + for the DDR_CONFIG register. Use this field to specify the register > + value as per the Hardware Programming Guide. > + > +- qcom,dll-config: Chipset and Platform specific value. Use this field to > + specify the DLL_CONFIG register value as per Hardware Programming Guide. Board specific or SoC specific? If the latter, imply this from the compatible string.