On Fri, May 15, 2020 at 05:40:50PM +0300, Andy Shevchenko wrote:
> On Fri, May 15, 2020 at 01:47:51PM +0300, Serge Semin wrote:
> > Tx-only DMA transfers are working perfectly fine since in this case
> > the code just ignores the Rx FIFO overflow interrupts. But it turns
> > out the SPI Rx-only transfers are broken since nothing pushing any
> > data to the shift registers, so the Rx FIFO is left empty and the
> > SPI core subsystems just returns a timeout error. Since DW DMAC
> > driver doesn't support something like cyclic write operations of
> > a single byte to a device register, the only way to support the
> > Rx-only SPI transfers is to fake it by using a dummy Tx-buffer.
> > This is what we intend to fix in this commit by setting the
> > SPI_CONTROLLER_MUST_TX flag for DMA-capable platform.

> I'm fine with this if Mark considers this right thing to do.
> So, conditionally
> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

Yes, this is good - it's quite a common issue that controllers have and
the main reason the flag exists is to provide a standard fix for it.