From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.6 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1954DC433E2 for ; Mon, 18 May 2020 15:19:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EDB4C20884 for ; Mon, 18 May 2020 15:19:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1589815192; bh=i/uWrEbUQkMdJDqHKyqNBwxmclbKqwRE5K2Wh7sf3lw=; h=Date:From:To:Cc:Subject:References:In-Reply-To:List-ID:From; b=N8OraO1MfuEhFoRoIECjckfcTTSsbqBAcMUbjZnSNC7avcaGzdE1xSwMLo5HxBPGy cqc+Qdq97Qgikg72a8Kq2F58+NV1kfsQwdjBKcCYlVX4lAigAD39X/mFZQWTrntlPc MpeZo5XfbRYZzhHZfamyGkNy0CVoidPbMoqcLzQ4= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728294AbgERPTu (ORCPT ); Mon, 18 May 2020 11:19:50 -0400 Received: from mail.kernel.org ([198.145.29.99]:57206 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727035AbgERPTu (ORCPT ); Mon, 18 May 2020 11:19:50 -0400 Received: from localhost (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 1018B206D4; Mon, 18 May 2020 15:19:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1589815189; bh=i/uWrEbUQkMdJDqHKyqNBwxmclbKqwRE5K2Wh7sf3lw=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=t//bgbOQF9M1/ae3klRD3yxL1s9QbAkBG0BDAyMMgG8u0T7F6ku9A3ZPEPbEbnHUn dQkx7u0efp+QbCYfjXcwyNKBkgEPCNdwAtHe7bPX5Fybgy1OVDEVN3HweiXKgjaTHk zSqjweZIDonDMPVvJ9OsrFxSO+0zupzkCzFfuWGc= Date: Mon, 18 May 2020 16:19:47 +0100 From: Mark Brown To: Serge Semin Cc: Serge Semin , Ramil Zaripov , Alexey Malahov , Thomas Bogendoerfer , Paul Burton , Ralf Baechle , Lee Jones , Miquel Raynal , Arnd Bergmann , Rob Herring , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, John Garry , Chuanhong Guo , Andy Shevchenko , Eddie James , Geert Uytterhoeven , Chris Packham , Tomer Maimon , Masahisa Kojima , Krzysztof Kozlowski , Florian Fainelli , Jassi Brar , linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org Subject: Re: [PATCH 2/2] spi: Add Baikal-T1 System Boot SPI Controller driver Message-ID: <20200518151946.GH8699@sirena.org.uk> References: <20200508093621.31619-1-Sergey.Semin@baikalelectronics.ru> <20200508093621.31619-3-Sergey.Semin@baikalelectronics.ru> <20200508113751.GD4820@sirena.org.uk> <20200510002039.hwahqasnnceowskz@mobilestation> <20200511212506.GA23852@sirena.org.uk> <20200518000542.ohtpem3lo2pbixbu@mobilestation> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="RwGu8mu1E+uYXPWP" Content-Disposition: inline In-Reply-To: <20200518000542.ohtpem3lo2pbixbu@mobilestation> X-Cookie: If in doubt, mumble. User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --RwGu8mu1E+uYXPWP Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, May 18, 2020 at 03:05:42AM +0300, Serge Semin wrote: > On Mon, May 11, 2020 at 10:25:06PM +0100, Mark Brown wrote: > > Yes, some flags should work here - the issue was that at least some > > controllers may end up trying to do multiple SPI operations for one > > spi-mem thing which will break if the chip select doesn't get changed to > > correspond with what's going on. > Ok. New SPI flag it is then. It will be something like this: > + #define SPI_CONTROLLER_FLASH_SS BIT(6) I'd rather use CS than SS (it's more common in the code). > So, what do you think? Should be fine, controllers that have an issue implementing just shouldn't set the flag. > > > > It's not clear to me that this hardware actually supports spi_mem in > > > > hardware? > > > SPI-mem operations are implemented by means of the EEPROM-read and Tx= -only > > > modes of the controller. > > Sure, but those seem like normal SPI-level things rather than cases > > where the hardware understands that it has a flash attached and is doing > > flash specific things. > No, hardware can't detect whether the flash is attached. This must be def= ined by > the platform, like based on the DT sub-nodes. This isn't about autodetection, it's about the abstraction level the hardware is operating on - some hardware is able to generate flash operations by itself (possibly with some help programming the opcodes that are needed by a given flash), some hardware just works at the bytestream level. > > A very common case for this stuff is that > > controllers have acceleration blocks for read and fall back on normal > > SPI for writes and erases, that sounds like what's going on here. >=20 > Well, yeah, they do provide some acceleration. EEPROM-read provides autom= atic > write-cmd-dummy-data-then-read operations. But in this case the only thin= g we > have to push into the SPI Tx FIFO is command and dummy bytes. The read op= eration So it's a write then read but you have to program the write each time? --RwGu8mu1E+uYXPWP Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEEreZoqmdXGLWf4p/qJNaLcl1Uh9AFAl7Cp5IACgkQJNaLcl1U h9CR+Qf9Ev6BSwOliLPeSLEND0J+GE/EF79DjdkufAO8e0ZfgAdIei5Jv7llRtTz ncbHQRBfSbB688/lo5AxDfB8StOMxBbCSLjxss4hLNNyaJio4JsaMLR0HwVKlUFz xg0KSY2wlhn4sveDiMldv69WVXzQMWI+Lq7Anjvjjaqb4IFU9JPNJtnJl5HOsUZE XrflFyIycmMwS21PAHWlDoG6NLnQ3P6Ko2BkwlbsJZh8dhcxUc8tdQGcTd2OoeeE BLXSqaEMqBrEFf3p9vJ7iDOy33fH6iNwVF05Z3E/Zz5080k9bLzqJtpViHS9NDp2 hfwjgB8qPJdtkJIagGX/nSbXgACk0Q== =Vs/w -----END PGP SIGNATURE----- --RwGu8mu1E+uYXPWP--