From: Andrew Morton <akpm@linux-foundation.org>
To: Bibo Mao <maobibo@loongson.cn>
Cc: "Thomas Bogendoerfer" <tsbogend@alpha.franken.de>,
"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
"Huacai Chen" <chenhc@lemote.com>,
"Paul Burton" <paulburton@kernel.org>,
"Dmitry Korotin" <dkorotin@wavecomp.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Stafford Horne" <shorne@gmail.com>,
"Steven Price" <steven.price@arm.com>,
"Anshuman Khandual" <anshuman.khandual@arm.com>,
linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org,
"Mike Rapoport" <rppt@linux.ibm.com>,
"Sergei Shtylyov" <sergei.shtylyov@cogentembedded.com>,
"Maciej W. Rozycki" <macro@wdc.com>,
linux-mm@kvack.org, "David Hildenbrand" <david@redhat.com>
Subject: Re: [PATCH v4 3/4] mm/memory.c: Add memory read privilege on page fault handling
Date: Tue, 19 May 2020 18:30:35 -0700 [thread overview]
Message-ID: <20200519183035.14fc56ba957266dde87a7778@linux-foundation.org> (raw)
In-Reply-To: <1589882610-7291-3-git-send-email-maobibo@loongson.cn>
On Tue, 19 May 2020 18:03:29 +0800 Bibo Mao <maobibo@loongson.cn> wrote:
> Here add pte_sw_mkyoung function to make page readable on MIPS
> platform during page fault handling. This patch improves page
> fault latency about 10% on my MIPS machine with lmbench
> lat_pagefault case.
>
> It is noop function on other arches, there is no negative
> influence on those architectures.
>
> --- a/arch/mips/include/asm/pgtable.h
> +++ b/arch/mips/include/asm/pgtable.h
> @@ -414,6 +414,8 @@ static inline pte_t pte_mkyoung(pte_t pte)
> return pte;
> }
>
> +#define pte_sw_mkyoung pte_mkyoung
> +
> #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
> static inline int pte_huge(pte_t pte) { return pte_val(pte) & _PAGE_HUGE; }
>
> --- a/include/asm-generic/pgtable.h
> +++ b/include/asm-generic/pgtable.h
> @@ -227,6 +227,21 @@ static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addres
> }
> #endif
>
> +/*
> + * On some architectures hardware does not set page access bit when accessing
> + * memory page, it is responsibilty of software setting this bit. It brings
> + * out extra page fault penalty to track page access bit. For optimization page
> + * access bit can be set during all page fault flow on these arches.
> + * To be differentiate with macro pte_mkyoung, this macro is used on platforms
> + * where software maintains page access bit.
> + */
> +#ifndef pte_sw_mkyoung
> +static inline pte_t pte_sw_mkyoung(pte_t pte)
> +{
> + return pte;
> +}
> +#endif
Yup, that's neat enough. Thanks for making this change. It looks like
all architectures include asm-generic/pgtable.h so that's fine.
It's conventional to add a
#define pte_sw_mkyoung pte_sw_mkyoung
immediately above the #endif there, so we can't try to implement
pte_sw_mkyoung() twice if this header gets included twice. But the
header has #ifndef _ASM_GENERIC_PGTABLE_H around the whole thing so
that should be OK.
next prev parent reply other threads:[~2020-05-20 1:30 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-19 10:03 [PATCH v4 1/4] MIPS: Do not flush tlb page when updating PTE entry Bibo Mao
2020-05-19 10:03 ` [PATCH v4 2/4] mm/memory.c: Update local TLB if PTE entry exists Bibo Mao
2020-05-20 1:26 ` Andrew Morton
2020-05-20 6:39 ` maobibo
2020-05-21 0:54 ` Andrew Morton
2020-05-19 10:03 ` [PATCH v4 3/4] mm/memory.c: Add memory read privilege on page fault handling Bibo Mao
2020-05-20 1:30 ` Andrew Morton [this message]
2020-05-20 8:22 ` maobibo
2020-05-19 10:03 ` [PATCH v4 4/4] MIPS: mm: add page valid judgement in function pte_modify Bibo Mao
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