linux-kernel.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Sean V Kelley <sean.v.kelley@linux.intel.com>
To: bhelgaas@google.com
Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
	Sean V Kelley <sean.v.kelley@linux.intel.com>
Subject: [PATCH V3 3/3] PCI: Add helpers to enable/disable CXL.mem and CXL.cache
Date: Wed, 20 May 2020 11:06:40 -0700	[thread overview]
Message-ID: <20200520180640.1911202-4-sean.v.kelley@linux.intel.com> (raw)
In-Reply-To: <20200520180640.1911202-1-sean.v.kelley@linux.intel.com>

With these helpers, a device driver can enable/disable access to
CXL.mem and CXL.cache. Note that the device driver is responsible for
managing the memory area.

Signed-off-by: Sean V Kelley <sean.v.kelley@linux.intel.com>
---
 drivers/pci/cxl.c | 84 +++++++++++++++++++++++++++++++++++++++++++++++
 drivers/pci/pci.h |  8 +++++
 2 files changed, 92 insertions(+)

diff --git a/drivers/pci/cxl.c b/drivers/pci/cxl.c
index 4497c597347f..e58e5262b59a 100644
--- a/drivers/pci/cxl.c
+++ b/drivers/pci/cxl.c
@@ -24,6 +24,90 @@
 #define PCI_CXL_HDM_COUNT(reg)		(((reg) & (3 << 4)) >> 4)
 #define PCI_CXL_VIRAL			BIT(14)
 
+#define PCI_CXL_CONFIG_LOCK		BIT(0)
+
+static void pci_cxl_unlock(struct pci_dev *dev)
+{
+	int cxl = dev->cxl_cap;
+	u16 lock;
+
+	pci_read_config_word(dev, cxl + PCI_CXL_LOCK, &lock);
+	lock &= ~PCI_CXL_CONFIG_LOCK;
+	pci_write_config_word(dev, cxl + PCI_CXL_LOCK, lock);
+}
+
+static void pci_cxl_lock(struct pci_dev *dev)
+{
+	int cxl = dev->cxl_cap;
+	u16 lock;
+
+	pci_read_config_word(dev, cxl + PCI_CXL_LOCK, &lock);
+	lock |= PCI_CXL_CONFIG_LOCK;
+	pci_write_config_word(dev, cxl + PCI_CXL_LOCK, lock);
+}
+
+/*
+ * CXL DVSEC CTRL registers have Read-Write-Lockable attributes.
+ * PCI_CXL_CONFIG_LOCK locks these CTRL registers by making them RO.
+ * This lock prevents future changes to configuration and is not intended
+ * for enforcing mutual exclusion. See CXL 1.1, sec 7.1.1.6
+ */
+static int pci_cxl_enable_disable_feature(struct pci_dev *dev, int enable,
+					  u16 feature)
+{
+	int cxl = dev->cxl_cap;
+	int ret;
+	u16 reg;
+
+	if (!dev->cxl_cap)
+		return -EINVAL;
+
+	/* Only for Device 0 Function 0, Root Complex Integrated Endpoints */
+	if (dev->devfn != 0 || (pci_pcie_type(dev) != PCI_EXP_TYPE_RC_END))
+		return -EINVAL;
+
+	pci_cxl_unlock(dev);
+	ret = pci_read_config_word(dev, cxl + PCI_CXL_CTRL, &reg);
+	if (ret)
+		goto lock;
+
+	if (enable)
+		reg |= feature;
+	else
+		reg &= ~feature;
+
+	ret = pci_write_config_word(dev, cxl + PCI_CXL_CTRL, reg);
+
+lock:
+	pci_cxl_lock(dev);
+
+	return ret;
+}
+
+int pci_cxl_mem_enable(struct pci_dev *dev)
+{
+	return pci_cxl_enable_disable_feature(dev, true, PCI_CXL_MEM);
+}
+EXPORT_SYMBOL_GPL(pci_cxl_mem_enable);
+
+void pci_cxl_mem_disable(struct pci_dev *dev)
+{
+	pci_cxl_enable_disable_feature(dev, false, PCI_CXL_MEM);
+}
+EXPORT_SYMBOL_GPL(pci_cxl_mem_disable);
+
+int pci_cxl_cache_enable(struct pci_dev *dev)
+{
+	return pci_cxl_enable_disable_feature(dev, true, PCI_CXL_CACHE);
+}
+EXPORT_SYMBOL_GPL(pci_cxl_cache_enable);
+
+void pci_cxl_cache_disable(struct pci_dev *dev)
+{
+	pci_cxl_enable_disable_feature(dev, false, PCI_CXL_CACHE);
+}
+EXPORT_SYMBOL_GPL(pci_cxl_cache_disable);
+
 /*
  * pci_find_cxl_capability - Identify and return offset to Vendor-Specific
  * capabilities.
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index d9905e2dee95..5ec7fa0eb709 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -472,8 +472,16 @@ static inline void pci_restore_ats_state(struct pci_dev *dev) { }
 #ifdef CONFIG_PCI_CXL
 /* Compute eXpress Link */
 void pci_cxl_init(struct pci_dev *dev);
+int pci_cxl_mem_enable(struct pci_dev *dev);
+void pci_cxl_mem_disable(struct pci_dev *dev);
+int pci_cxl_cache_enable(struct pci_dev *dev);
+void pci_cxl_cache_disable(struct pci_dev *dev);
 #else
 static inline void pci_cxl_init(struct pci_dev *dev) { }
+static inline int pci_cxl_mem_enable(struct pci_dev *dev) { return 0; }
+static inline void pci_cxl_mem_disable(struct pci_dev *dev) { }
+static inline int pci_cxl_cache_enable(struct pci_dev *dev) { return 0; }
+static inline void pci_cxl_cache_disable(struct pci_dev *dev) { }
 #endif
 
 #ifdef CONFIG_PCI_PRI
-- 
2.26.2


      parent reply	other threads:[~2020-05-20 18:06 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-20 18:06 [PATCH V3 0/3] PCI: Add basic Compute eXpress Link DVSEC decode Sean V Kelley
2020-05-20 18:06 ` [PATCH V3 1/3] PCI: Add defines for Designated Vendor-Specific Capability Sean V Kelley
2020-05-20 18:06 ` [PATCH V3 2/3] PCI: Add basic Compute eXpress Link DVSEC decode Sean V Kelley
2020-05-20 18:06 ` Sean V Kelley [this message]

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20200520180640.1911202-4-sean.v.kelley@linux.intel.com \
    --to=sean.v.kelley@linux.intel.com \
    --cc=bhelgaas@google.com \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).