From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8CD22C433E0 for ; Thu, 21 May 2020 17:50:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6112D20759 for ; Thu, 21 May 2020 17:50:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="mX0Tp9zE" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729998AbgEURuH (ORCPT ); Thu, 21 May 2020 13:50:07 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:57762 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730254AbgEURsl (ORCPT ); Thu, 21 May 2020 13:48:41 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 04LHmZWk052539; Thu, 21 May 2020 12:48:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1590083315; bh=oP5/4iAxad86JB5Vq5xypRCcIfd0uO0QCRiPzAP7S7Y=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=mX0Tp9zEAxKflpHQSBLhIGx9kQfkTko2hobicymaj2s/XyROUc51DgxJZnounruN3 8elPPqBJ7zSD0rrM24fRVYy8kyrvhi8Uwkvy+LYfgL6ZKd+8tCPJcZ2kzg7jSjqNAd 0HY4Qu0tEKR5zwtFEkIQHeq2yZUpZJ1FUt7pm6bE= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id 04LHmZPP120116; Thu, 21 May 2020 12:48:35 -0500 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 21 May 2020 12:48:35 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 21 May 2020 12:48:35 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 04LHmZeJ038639; Thu, 21 May 2020 12:48:35 -0500 From: Dan Murphy To: , , , , CC: , , , Dan Murphy Subject: [RFC PATCH net-next 1/4] dt-bindings: net: Add tx and rx internal delays Date: Thu, 21 May 2020 12:48:31 -0500 Message-ID: <20200521174834.3234-2-dmurphy@ti.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200521174834.3234-1-dmurphy@ti.com> References: <20200521174834.3234-1-dmurphy@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org tx-internal-delays and rx-internal-delays are a common setting for RGMII capable devices. These properties are used when the phy-mode or phy-controller is set to rgmii-id, rgmii-rxid or rgmii-txid. These modes indicate to the controller that the PHY will add the internal delay for the connection. Signed-off-by: Dan Murphy --- .../bindings/net/ethernet-controller.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/net/ethernet-controller.yaml b/Documentation/devicetree/bindings/net/ethernet-controller.yaml index ac471b60ed6a..3f25066c339c 100644 --- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml @@ -143,6 +143,20 @@ properties: Specifies the PHY management type. If auto is set and fixed-link is not specified, it uses MDIO for management. + rx-internal-delay: + $ref: /schemas/types.yaml#definitions/uint32 + description: | + RGMII Receive PHY Clock Delay defined in pico seconds. This is used for + PHY's that have configurable RX internal delays. This property is only + used when the phy-mode or phy-connection-type is rgmii-id or rgmii-rxid. + + tx-internal-delay: + $ref: /schemas/types.yaml#definitions/uint32 + description: | + RGMII Transmit PHY Clock Delay defined in pico seconds. This is used for + PHY's that have configurable TX internal delays. This property is only + used when the phy-mode or phy-connection-type is rgmii-id or rgmii-txid. + fixed-link: allOf: - if: -- 2.26.2