From: Jonathan Marek <jonathan@marek.ca>
To: linux-arm-msm@vger.kernel.org
Cc: Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND
FLATTENED DEVICE TREE BINDINGS),
linux-kernel@vger.kernel.org (open list)
Subject: [PATCH 10/10] arm64: dts: qcom: add sm8250 GPU nodes
Date: Sun, 24 May 2020 17:06:11 -0400 [thread overview]
Message-ID: <20200524210615.17035-11-jonathan@marek.ca> (raw)
In-Reply-To: <20200524210615.17035-1-jonathan@marek.ca>
This brings up the GPU. Tested on HDK865 by running vulkan CTS.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 139 +++++++++++++++++++++++++++
1 file changed, 139 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 3bdce658c08a..a55d0e5d7425 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -5,6 +5,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-sm8250.h>
+#include <dt-bindings/clock/qcom,gpucc-sm8250.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
@@ -387,6 +388,144 @@ tcsr_mutex: hwlock@1f40000 {
#hwlock-cells = <1>;
};
+ gpu: gpu@3d00000 {
+ /*
+ * note: the amd,imageon compatible makes it possible
+ * to use the drm/msm driver without the display node,
+ * make sure to remove it when display node is added
+ */
+ compatible = "qcom,adreno-650.2",
+ "qcom,adreno",
+ "amd,imageon";
+ #stream-id-cells = <16>;
+
+ reg = <0 0x3d00000 0 0x40000>;
+ reg-names = "kgsl_3d0_reg_memory";
+
+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+
+ iommus = <&adreno_smmu 0 0x401>;
+
+ operating-points-v2 = <&gpu_opp_table>;
+
+ qcom,gmu = <&gmu>;
+
+ zap-shader {
+ memory-region = <&gpu_mem>;
+ };
+
+ /* note: downstream checks gpu binning for 670 Mhz */
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-670000000 {
+ opp-hz = /bits/ 64 <670000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ };
+
+ opp-587000000 {
+ opp-hz = /bits/ 64 <587000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ };
+
+ opp-525000000 {
+ opp-hz = /bits/ 64 <525000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+ };
+
+ opp-490000000 {
+ opp-hz = /bits/ 64 <490000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ };
+
+ /* opp-441600000 {
+ opp-hz = /bits/ 64 <441600000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
+ }; */
+
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ opp-305000000 {
+ opp-hz = /bits/ 64 <305000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+ };
+ };
+
+ gmu: gmu@3d6a000 {
+ compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
+
+ reg = <0 0x3d6a000 0 0x30000>,
+ <0 0x3de0000 0 0x10000>,
+ <0 0xb290000 0 0x10000>,
+ <0 0xb490000 0 0x10000>;
+ reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
+
+ interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hfi", "gmu";
+
+ clocks = <&gpucc GPU_CC_AHB_CLK>,
+ <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_CXO_CLK>,
+ <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
+ clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
+
+ power-domains = <&gpucc GPU_CX_GDSC>,
+ <&gpucc GPU_GX_GDSC>;
+ power-domain-names = "cx", "gx";
+
+ iommus = <&adreno_smmu 5 0x400>;
+
+ operating-points-v2 = <&gmu_opp_table>;
+
+ gmu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+ };
+ };
+ };
+
+ gpucc: clock-controller@3d90000 {
+ compatible = "qcom,sm8250-gpucc";
+ reg = <0 0x3d90000 0 0x9000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+ };
+
+ adreno_smmu: iommu@3da0000 {
+ compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
+ reg = <0 0x3da0000 0 0x10000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <2>;
+ interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gpucc GPU_CC_AHB_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
+ clock-names = "ahb", "bus", "iface";
+
+ power-domains = <&gpucc GPU_CX_GDSC>;
+ };
+
usb_1_hsphy: phy@88e3000 {
compatible = "qcom,sm8250-usb-hs-phy",
"qcom,usb-snps-hs-7nm-phy";
--
2.26.1
prev parent reply other threads:[~2020-05-24 21:06 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-24 21:06 [PATCH 00/10] Enable GPU for SM8150 and SM8250 Jonathan Marek
2020-05-24 21:06 ` [PATCH 01/10] clk: qcom: clk-alpha-pll: remove unused/incorrect PLL_CAL_VAL Jonathan Marek
2020-05-26 23:21 ` Stephen Boyd
2020-05-26 23:30 ` Jonathan Marek
2020-05-27 2:42 ` Stephen Boyd
2020-05-24 21:06 ` [PATCH 02/10] clk: qcom: clk-alpha-pll: same regs and ops for trion and lucid Jonathan Marek
2020-05-24 21:06 ` [PATCH 03/10] clk: qcom: clk-alpha-pll: use the right PCAL_DONE value for lucid pll Jonathan Marek
2020-05-24 21:06 ` [PATCH 04/10] clk: qcom: gcc: remove unnecessary vco_table from SM8150 Jonathan Marek
2020-05-24 21:06 ` [PATCH 05/10] dt-bindings: clock: Introduce SM8150 QCOM Graphics clock bindings Jonathan Marek
2020-05-28 23:41 ` Rob Herring
2020-05-24 21:06 ` [PATCH 06/10] dt-bindings: clock: Introduce SM8250 " Jonathan Marek
2020-05-24 21:06 ` [PATCH 07/10] clk: qcom: Add graphics clock controller driver for SM8150 Jonathan Marek
2020-05-27 8:44 ` Stephen Boyd
2020-06-29 17:27 ` Jonathan Marek
2020-05-24 21:06 ` [PATCH 08/10] clk: qcom: Add graphics clock controller driver for SM8250 Jonathan Marek
2020-05-25 9:47 ` Sai Prakash Ranjan
2020-05-29 1:11 ` Bjorn Andersson
2020-05-29 6:56 ` Sai Prakash Ranjan
2020-06-03 18:09 ` Bjorn Andersson
2020-06-03 18:20 ` Sai Prakash Ranjan
2020-05-24 21:06 ` [PATCH 09/10] arm64: dts: qcom: add sm8150 GPU nodes Jonathan Marek
2020-05-24 21:06 ` Jonathan Marek [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200524210615.17035-11-jonathan@marek.ca \
--to=jonathan@marek.ca \
--cc=agross@kernel.org \
--cc=bjorn.andersson@linaro.org \
--cc=devicetree@vger.kernel.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=robh+dt@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).