From: Peter Zijlstra <peterz@infradead.org>
To: Andi Kleen <andi@firstfloor.org>
Cc: Kees Cook <keescook@chromium.org>,
Greg KH <gregkh@linuxfoundation.org>,
x86@kernel.org, linux-kernel@vger.kernel.org, sashal@kernel.org,
Andi Kleen <ak@linux.intel.com>,
stable@vger.kernel.org
Subject: Re: [PATCH v1] x86: Pin cr4 FSGSBASE
Date: Wed, 27 May 2020 12:31:47 +0200 [thread overview]
Message-ID: <20200527103147.GI325280@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <20200526231423.qcsolcpll534sgro@two.firstfloor.org>
On Tue, May 26, 2020 at 04:14:25PM -0700, Andi Kleen wrote:
> > And if this is going to be more permanent, we can separate the mask
> > (untested):
>
> The FSGSBASE one should not be permanent, it will be replaced
> with the full FSGSBASE patches that set that bit correctly.
Well, even with full FSGSBASE patches on, that CR4 bit should never get
changed after boot.
prev parent reply other threads:[~2020-05-27 10:34 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-26 5:28 [PATCH v1] x86: Pin cr4 FSGSBASE Andi Kleen
2020-05-26 6:56 ` Greg KH
2020-05-26 7:57 ` Peter Zijlstra
2020-05-26 8:17 ` Greg KH
2020-05-26 9:17 ` Peter Zijlstra
2020-05-26 10:16 ` Greg KH
2020-05-26 15:48 ` Andi Kleen
2020-05-26 16:20 ` Kees Cook
2020-05-26 16:32 ` Greg KH
2020-05-26 17:24 ` Wojtek Porczyk
2020-05-27 7:07 ` Greg KH
2020-05-27 10:58 ` Wojtek Porczyk
2020-05-26 16:15 ` Kees Cook
2020-05-26 21:16 ` Greg KH
2020-05-26 16:38 ` Kees Cook
2020-05-26 23:14 ` Andi Kleen
2020-05-27 10:31 ` Peter Zijlstra [this message]
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