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Sat, 30 May 2020 10:07:52 +0000 From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Albert Ou , Daniel Lezcano , Thomas Gleixner , Jason Cooper , Marc Zyngier Cc: Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v6 0/6] New RISC-V Local Interrupt Controller Driver Date: Sat, 30 May 2020 15:37:19 +0530 Message-Id: <20200530100725.265481-1-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: MAXPR0101CA0037.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:d::23) To DM6PR04MB6201.namprd04.prod.outlook.com (2603:10b6:5:127::32) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (49.207.61.131) by MAXPR0101CA0037.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:d::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3045.21 via Frontend Transport; Sat, 30 May 2020 10:07:48 +0000 X-Mailer: git-send-email 2.25.1 X-Originating-IP: [49.207.61.131] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 01e3b737-5c8e-4ce1-b8e6-08d804815059 X-MS-TrafficTypeDiagnostic: DM6PR04MB4314: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: WDCIPOUTBOUND: EOP-TRUE X-MS-Oob-TLC-OOBClassifiers: OLM:8882; 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X-MS-Exchange-AntiSpam-MessageData: +mW4zNRGJGeXJnH+W/vk0tFdMucMX+//CkCNRcaRtNpsrsg7a36j459gXEZm3jt7vEGaLkq56h1/fj+gyHFHW9x61EFuolXGk5pVY+VdD+qdUs4GGsGlUEd+WiQsD0VN/ZVGucorUqTMEkY2PY2b0D19RlwVzkDMKyBqdd4W20RR4zxVEhY2lLM7ewg66m42ATGbTcTmn3yjwcS8cBmpY8kxA7afPgCEAgnrFy7WqSD1o84X33PPyOfDAWh2eCla45z/qoGwSWZbhqdDAHDW1nQzJgqRBTDrS+0CfPM8ezZcODFwamOhblH7QDmuAC1BRXFjXRgfDTFZ/S/mK6QTn2MAXLumi0JX25mKcEYOydMjS0C/Gk7L8PaCyQAxG1zkpRVhIBVcO7EopWAvJmi8yNoGdWWMTpArwbgI0CFxlPSFyy05CTYLiEXz7brRk5H690bnL4tY3ncRjKTpzIGYabNaE62w13zcvOE7pfBzpE9t58sIh9g8Su6ebmjXtaBT X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 01e3b737-5c8e-4ce1-b8e6-08d804815059 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 May 2020 10:07:52.0213 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: D5FLIXEHSmIa6pBI18E2pP6gOKP2uzbEPB9jenzpoHuZzz4ew4nb2waHYNCqmnn8YifmJiBJt1OuMaWOMWbFBQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR04MB4314 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patchset provides a new RISC-V Local Interrupt Controller Driver for managing per-CPU local interrupts. The overall approach is inspired from the way per-CPU local interrupts are handled by Linux ARM64 and ARM GICv3 driver. Few advantages of this new driver over previous one are: 1. All local interrupts are registered as per-CPU interrupts 2. The RISC-V timer driver can register timer interrupt handler using kernel irq subsystem without relying on arch/riscv to explicitly call it's interrupt handler 3. The KVM RISC-V can use this driver to implement interrupt handler for per-HART guest external interrupt defined by the RISC-V H-Extension 4. In future, we can develop drivers for devices with per-HART interrupts without changing arch code or this driver (example, CLINT timer driver for RISC-V M-mode kernel) With this patchset, output of "cat /proc/interrupts" looks as follows: CPU0 CPU1 CPU2 CPU3 2: 379 0 0 0 SiFive PLIC 10 ttyS0 3: 591 0 0 0 SiFive PLIC 8 virtio0 5: 5079 10821 8435 12984 RISC-V INTC 5 riscv-timer IPI0: 2045 2537 891 870 Rescheduling interrupts IPI1: 9 269 91 168 Function call interrupts IPI2: 0 0 0 0 CPU stop interrupts The patchset is based up Linux-5.7-rc7 and can be found at riscv_intc_v6 branch of: https://github.com/avpatel/linux.git This series is tested on: 1. QEMU RV64 virt machine using Linux RISC-V S-mode 2. QEMU RV32 virt machine using Linux RISC-V S-mode 3. QEMU RV64 virt machine using Linux RISC-V M-mode (i.e. NoMMU) Changes since v5: - Rebased to Linux-5.7-rc7 with PLIC improvement patches - Removed riscv_of_parent_hartid() from PATCH3 - Addressed other minor comments from Palmer and Marc Z Changes since v4: - Rebased to Linux-5.7-rc6 and multi-PLIC improvement patches - Added separate patch to force select RISCV_INTC for CONFIG_RISCV - Fixed the driver for Linux RISC-V NoMMU Changes since v3: - Rebased to Linux-5.6-rc5 and Atish's PLIC patches - Added separate patch to rename and move plic_find_hart_id() to arch directory - Use riscv_of_parent_hartid() in riscv_intc_init() instead of atomic counter Changes since v2: - Dropped PATCH2 since it was merged long-time back - Rebased series from Linux-4.19-rc2 to Linux-5.6-rc2 Changes since v1: - Removed changes related to puggable IPI triggering - Separate patch for self-contained IPI handling routine - Removed patch for GENERIC_IRQ kconfig options - Added patch to remove do_IRQ() function - Rebased upon Atish's SMP patches Anup Patel (6): RISC-V: self-contained IPI handling routine RISC-V: Rename and move plic_find_hart_id() to arch directory irqchip: RISC-V per-HART local interrupt controller driver clocksource/drivers/timer-riscv: Use per-CPU timer interrupt RISC-V: Remove do_IRQ() function RISC-V: Force select RISCV_INTC for CONFIG_RISCV arch/riscv/Kconfig | 2 + arch/riscv/include/asm/irq.h | 5 -- arch/riscv/include/asm/processor.h | 1 + arch/riscv/include/asm/smp.h | 3 + arch/riscv/kernel/cpu.c | 16 ++++ arch/riscv/kernel/entry.S | 4 +- arch/riscv/kernel/irq.c | 33 +------ arch/riscv/kernel/smp.c | 11 ++- arch/riscv/kernel/traps.c | 2 - drivers/clocksource/timer-riscv.c | 41 ++++++++- drivers/irqchip/Kconfig | 13 +++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-riscv-intc.c | 140 +++++++++++++++++++++++++++++ drivers/irqchip/irq-sifive-plic.c | 44 ++++----- include/linux/cpuhotplug.h | 1 + 15 files changed, 253 insertions(+), 64 deletions(-) create mode 100644 drivers/irqchip/irq-riscv-intc.c -- 2.25.1