[PATCH RESEND v2 0/6] mips: Add DT bindings for MIPS CDMM and MIPS GIC

[PATCH RESEND v2 0/6] mips: Add DT bindings for MIPS CDMM and MIPS GIC

[Serge Semin]

Folks, the code and DT-related patches here have been mostly reviewed.
Please consider merge the series in or at least give me a feedback to
update the series, since merge window is getting opened tomorrow and I
would really appreciate to see the leftover being merged in.

Regarding this patchset origin. Recently I've submitted a series of
patchset's which provided multiple fixes for the MIPS arch subsystem and
the MIPS GIC and DW APB Timer drivers, which were required for the
Baikal-T1 SoC correctly working with those drivers. Mostly those patchsets
have been already merged into the corresponding subsystems, but several
patches have been left floating since noone really responded for review
except Rob provided his approval regarding DT bindings. Thus in this
patchset I've collected all the leftovers so not to loose them in a pale
of the maintainers email logs.

The patchset includes the following updates: MIPS CPC and GIC DT bindings
legacy text-based file are converted to the DT schema (Rob has already
reviewed them), add MIPS CDMM DT node support to place the CDMM block at
the platform-specific MMIO range, make sure MIPS CDMM is available for
MIPS_R5 CPUs.

Seeing the series concerns the MIPS-related drivers it's better to merge
it in through the MIPS repository:
https://git.kernel.org/pub/scm/linux/kernel/git/mips/linux.git/

This patchset is rebased and tested on the mainline Linux kernel 5.7-rc4:
base-commit: 0e698dfa2822 ("Linux 5.7-rc4")
tag: v5.7-rc4

Suggestion.
Since Paul isn't looking after the MIPS arch code anymore, Ralf hasn't
been seen maintaining MIPS for a long time, Thomas is only responsible
for the next part of it:
	F:      Documentation/devicetree/bindings/mips/
	F:      Documentation/mips/
	F:      arch/mips/
	F:      drivers/platform/mips/
the MIPS-specific drivers like:
	F:	drivers/bus/mips_cdmm.c
	F:	drivers/irqchip/irq-mips-cpu.c
	F:	drivers/irqchip/irq-mips-gic.c
	F:	drivers/clocksource/mips-gic-timer.c
	F:	drivers/cpuidle/cpuidle-cps.c
seem to be left for the subsystems maintainers to support. So if you don't
mind or unless there is a better alternative, I can help with looking
after them to ease the maintainers review burden and since I'll be working
on our MIPS-based SoC drivers integrating into the mainline kernel repo
anyway. If you don't like this idea, please just decline the last
patch in the series.

Previous patchsets:
mips: Prepare MIPS-arch code for Baikal-T1 SoC support:
Link: https://lore.kernel.org/linux-mips/20200306124807.3596F80307C2@mail.baikalelectronics.ru
Link: https://lore.kernel.org/linux-mips/20200506174238.15385-1-Sergey.Semin@baikalelectronics.ru
Link: https://lore.kernel.org/linux-mips/20200521140725.29571-1-Sergey.Semin@baikalelectronics.ru

clocksource: Fix MIPS GIC and DW APB Timer for Baikal-T1 SoC support:
Link: https://lore.kernel.org/linux-rtc/20200324174325.14213-1-Sergey.Semin@baikalelectronics.ru
Link: https://lore.kernel.org/linux-rtc/20200506214107.25956-1-Sergey.Semin@baikalelectronics.ru
Link: https://lore.kernel.org/linux-rtc/20200521005321.12129-1-Sergey.Semin@baikalelectronics.ru

Changelog prev:
- Add yaml-based bindings file for MIPS CDMM dt-node.
- Convert mti,mips-cpc to DT schema.
- Use a shorter summary describing the bindings modification patches.
- Rearrange the SoBs with adding Alexey' co-development tag.
- Lowercase the hex numbers in the dt-bindings.

Changelog v2:
- Resend.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <maz@kernel.org>
Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org

Serge Semin (6):
  dt-bindings: power: Convert mti,mips-cpc to DT schema
  dt-bindings: interrupt-controller: Convert mti,gic to DT schema
  dt-bindings: bus: Add MIPS CDMM controller
  mips: cdmm: Add mti,mips-cdmm dtb node support
  bus: cdmm: Add MIPS R5 arch support
  MAINTAINERS: Add maintainers for MIPS core drivers

 .../bindings/bus/mti,mips-cdmm.yaml           |  35 +++++
 .../interrupt-controller/mips-gic.txt         |  67 --------
 .../interrupt-controller/mti,gic.yaml         | 148 ++++++++++++++++++
 .../bindings/power/mti,mips-cpc.txt           |   8 -
 .../bindings/power/mti,mips-cpc.yaml          |  35 +++++
 MAINTAINERS                                   |  10 ++
 drivers/bus/Kconfig                           |   2 +-
 drivers/bus/mips_cdmm.c                       |  15 ++
 8 files changed, 244 insertions(+), 76 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/bus/mti,mips-cdmm.yaml
 delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml
 delete mode 100644 Documentation/devicetree/bindings/power/mti,mips-cpc.txt
 create mode 100644 Documentation/devicetree/bindings/power/mti,mips-cpc.yaml

-- 
2.26.2

[PATCH v2 1/6] dt-bindings: power: Convert mti,mips-cpc to DT schema

[Serge Semin]

It's a Cluster Power Controller embedded into the MIPS IP cores.
Currently the corresponding dts node is supposed to have compatible
and reg properties.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Rob Herring <robh@kernel.org>

---

Changelog prev:
- Reword the changelog summary - use shorter version.
- Lowercase the example hex'es.
---
 .../bindings/power/mti,mips-cpc.txt           |  8 -----
 .../bindings/power/mti,mips-cpc.yaml          | 35 +++++++++++++++++++
 2 files changed, 35 insertions(+), 8 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/power/mti,mips-cpc.txt
 create mode 100644 Documentation/devicetree/bindings/power/mti,mips-cpc.yaml

diff --git a/Documentation/devicetree/bindings/power/mti,mips-cpc.txt b/Documentation/devicetree/bindings/power/mti,mips-cpc.txt
deleted file mode 100644
index c6b82511ae8a..000000000000
--- a/Documentation/devicetree/bindings/power/mti,mips-cpc.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-Binding for MIPS Cluster Power Controller (CPC).
-
-This binding allows a system to specify where the CPC registers are
-located.
-
-Required properties:
-compatible : Should be "mti,mips-cpc".
-regs: Should describe the address & size of the CPC register region.
diff --git a/Documentation/devicetree/bindings/power/mti,mips-cpc.yaml b/Documentation/devicetree/bindings/power/mti,mips-cpc.yaml
new file mode 100644
index 000000000000..9cd92a57130c
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/mti,mips-cpc.yaml
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/mti,mips-cpc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MIPS Cluster Power Controller
+
+description: |
+  Defines a location of the MIPS Cluster Power Controller registers.
+
+maintainers:
+  - Paul Burton <paulburton@kernel.org>
+
+properties:
+  compatible:
+    const: mti,mips-cpc
+
+  reg:
+    description: |
+      Base address and size of an unoccupied memory region, which will be
+      used to map the MIPS CPC registers block.
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+examples:
+  - |
+    cpc@1bde0000 {
+      compatible = "mti,mips-cpc";
+      reg = <0 0x1bde0000 0 0x8000>;
+    };
+...
-- 
2.26.2

[PATCH v2 2/6] dt-bindings: interrupt-controller: Convert mti,gic to DT schema

[Serge Semin]

Modern device tree bindings are supposed to be created as YAML-files
in accordance with DT schema. This commit replaces MIPS GIC legacy bare
text binding with YAML file. As before the binding file states that the
corresponding dts node is supposed to be compatible with MIPS Global
Interrupt Controller indicated by the "mti,gic" compatible string and
to provide a mandatory interrupt-controller and '#interrupt-cells'
properties. There might be optional registers memory range,
"mti,reserved-cpu-vectors" and "mti,reserved-ipi-vectors" properties
specified.

MIPS GIC also includes a free-running global timer, per-CPU count/compare
timers, and a watchdog. Since currently the GIC Timer is only supported the
DT schema expects an IRQ and clock-phandler charged timer sub-node with
"mti,mips-gic-timer" compatible string.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Rob Herring <robh@kernel.org>

---

I don't really know who is the corresponding driver maintainer, so I
added Paul to the maintainers property since he used to be looking for the
MIPS arch and Thomas looking after it now. Any idea what email should be
specified there instead?

Changelog prev:
- Since timer sub-node has no unit-address, the node shouldn't be named
  with one. So alter the MIPS GIC bindings to have a pure "timer"
  sub-node.
- Discard allOf: [ $ref: /schemas/interrupt-controller.yaml# ].
- Since it's a conversion patch use GPL-2.0-only SPDX header.
---
 .../interrupt-controller/mips-gic.txt         |  67 --------
 .../interrupt-controller/mti,gic.yaml         | 148 ++++++++++++++++++
 2 files changed, 148 insertions(+), 67 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml

diff --git a/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt b/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
deleted file mode 100644
index 173595305e26..000000000000
--- a/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
+++ /dev/null
@@ -1,67 +0,0 @@
-MIPS Global Interrupt Controller (GIC)
-
-The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
-It also supports local (per-processor) interrupts and software-generated
-interrupts which can be used as IPIs.  The GIC also includes a free-running
-global timer, per-CPU count/compare timers, and a watchdog.
-
-Required properties:
-- compatible : Should be "mti,gic".
-- interrupt-controller : Identifies the node as an interrupt controller
-- #interrupt-cells : Specifies the number of cells needed to encode an
-  interrupt specifier.  Should be 3.
-  - The first cell is the type of interrupt, local or shared.
-    See <include/dt-bindings/interrupt-controller/mips-gic.h>.
-  - The second cell is the GIC interrupt number.
-  - The third cell encodes the interrupt flags.
-    See <include/dt-bindings/interrupt-controller/irq.h> for a list of valid
-    flags.
-
-Optional properties:
-- reg : Base address and length of the GIC registers.  If not present,
-  the base address reported by the hardware GCR_GIC_BASE will be used.
-- mti,reserved-cpu-vectors : Specifies the list of CPU interrupt vectors
-  to which the GIC may not route interrupts.  Valid values are 2 - 7.
-  This property is ignored if the CPU is started in EIC mode.
-- mti,reserved-ipi-vectors : Specifies the range of GIC interrupts that are
-  reserved for IPIs.
-  It accepts 2 values, the 1st is the starting interrupt and the 2nd is the size
-  of the reserved range.
-  If not specified, the driver will allocate the last 2 * number of VPEs in the
-  system.
-
-Required properties for timer sub-node:
-- compatible : Should be "mti,gic-timer".
-- interrupts : Interrupt for the GIC local timer.
-
-Optional properties for timer sub-node:
-- clocks : GIC timer operating clock.
-- clock-frequency : Clock frequency at which the GIC timers operate.
-
-Note that one of clocks or clock-frequency must be specified.
-
-Example:
-
-	gic: interrupt-controller@1bdc0000 {
-		compatible = "mti,gic";
-		reg = <0x1bdc0000 0x20000>;
-
-		interrupt-controller;
-		#interrupt-cells = <3>;
-
-		mti,reserved-cpu-vectors = <7>;
-		mti,reserved-ipi-vectors = <40 8>;
-
-		timer {
-			compatible = "mti,gic-timer";
-			interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
-			clock-frequency = <50000000>;
-		};
-	};
-
-	uart@18101400 {
-		...
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
-		...
-	};
diff --git a/Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml b/Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml
new file mode 100644
index 000000000000..9f0eb3addac4
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml
@@ -0,0 +1,148 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MIPS Global Interrupt Controller
+
+maintainers:
+  - Paul Burton <paulburton@kernel.org>
+  - Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+
+description: |
+  The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
+  It also supports local (per-processor) interrupts and software-generated
+  interrupts which can be used as IPIs. The GIC also includes a free-running
+  global timer, per-CPU count/compare timers, and a watchdog.
+
+properties:
+  compatible:
+    const: mti,gic
+
+  "#interrupt-cells":
+    const: 3
+    description: |
+      The 1st cell is the type of interrupt: local or shared defined in the
+      file 'dt-bindings/interrupt-controller/mips-gic.h'. The 2nd cell is the
+      GIC interrupt number. The 3d cell encodes the interrupt flags setting up
+      the IRQ trigger modes, which are defined in the file
+      'dt-bindings/interrupt-controller/irq.h'.
+
+  reg:
+    description: |
+      Base address and length of the GIC registers space. If not present,
+      the base address reported by the hardware GCR_GIC_BASE will be used.
+    maxItems: 1
+
+  interrupt-controller: true
+
+  mti,reserved-cpu-vectors:
+    description: |
+      Specifies the list of CPU interrupt vectors to which the GIC may not
+      route interrupts. This property is ignored if the CPU is started in EIC
+      mode.
+    allOf:
+      - $ref: /schemas/types.yaml#definitions/uint32-array
+      - minItems: 1
+        maxItems: 6
+        uniqueItems: true
+        items:
+          minimum: 2
+          maximum: 7
+
+  mti,reserved-ipi-vectors:
+    description: |
+      Specifies the range of GIC interrupts that are reserved for IPIs.
+      It accepts two values: the 1st is the starting interrupt and the 2nd is
+      the size of the reserved range. If not specified, the driver will
+      allocate the last (2 * number of VPEs in the system).
+    allOf:
+      - $ref: /schemas/types.yaml#definitions/uint32-array
+      - items:
+          - minimum: 0
+            maximum: 254
+          - minimum: 2
+            maximum: 254
+
+  timer:
+    type: object
+    description: |
+      MIPS GIC includes a free-running global timer, per-CPU count/compare
+      timers, and a watchdog. Currently only the GIC Timer is supported.
+    properties:
+      compatible:
+        const: mti,gic-timer
+
+      interrupts:
+        description: |
+          Interrupt for the GIC local timer, so normally it's suppose to be of
+          <GIC_LOCAL X IRQ_TYPE_NONE> format.
+        maxItems: 1
+
+      clocks:
+        maxItems: 1
+
+      clock-frequency: true
+
+    required:
+      - compatible
+      - interrupts
+
+    oneOf:
+      - required:
+          - clocks
+      - required:
+          - clock-frequency
+
+    additionalProperties: false
+
+unevaluatedProperties: false
+
+required:
+  - compatible
+  - "#interrupt-cells"
+  - interrupt-controller
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/mips-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    interrupt-controller@1bdc0000 {
+      compatible = "mti,gic";
+      reg = <0x1bdc0000 0x20000>;
+      interrupt-controller;
+      #interrupt-cells = <3>;
+      mti,reserved-cpu-vectors = <7>;
+      mti,reserved-ipi-vectors = <40 8>;
+
+      timer {
+        compatible = "mti,gic-timer";
+        interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
+        clock-frequency = <50000000>;
+      };
+    };
+  - |
+    #include <dt-bindings/interrupt-controller/mips-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    interrupt-controller@1bdc0000 {
+      compatible = "mti,gic";
+      reg = <0x1bdc0000 0x20000>;
+      interrupt-controller;
+      #interrupt-cells = <3>;
+
+      timer {
+        compatible = "mti,gic-timer";
+        interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
+        clocks = <&cpu_pll>;
+      };
+    };
+  - |
+    interrupt-controller {
+      compatible = "mti,gic";
+      interrupt-controller;
+      #interrupt-cells = <3>;
+    };
+...
-- 
2.26.2

[PATCH v2 3/6] dt-bindings: bus: Add MIPS CDMM controller

[Serge Semin]

It's a Common Device Memory Map controller embedded into the MIPS IP
cores, which dts node is supposed to have compatible and reg properties.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Rob Herring <robh@kernel.org>

---

Changelog prev:
- Lowercase the example hex'es.
---
 .../bindings/bus/mti,mips-cdmm.yaml           | 35 +++++++++++++++++++
 1 file changed, 35 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/bus/mti,mips-cdmm.yaml

diff --git a/Documentation/devicetree/bindings/bus/mti,mips-cdmm.yaml b/Documentation/devicetree/bindings/bus/mti,mips-cdmm.yaml
new file mode 100644
index 000000000000..b3ba98515cbe
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/mti,mips-cdmm.yaml
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bus/mti,mips-cdmm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MIPS Common Device Memory Map
+
+description: |
+  Defines a location of the MIPS Common Device Memory Map registers.
+
+maintainers:
+  - James Hogan <jhogan@kernel.org>
+
+properties:
+  compatible:
+    const: mti,mips-cdmm
+
+  reg:
+    description: |
+      Base address and size of an unoccupied memory region, which will be
+      used to map the MIPS CDMM registers block.
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+examples:
+  - |
+    cdmm@1bde8000 {
+      compatible = "mti,mips-cdmm";
+      reg = <0 0x1bde8000 0 0x8000>;
+    };
+...
-- 
2.26.2

[PATCH v2 4/6] mips: cdmm: Add mti,mips-cdmm dtb node support

[Serge Semin]

Since having and mapping the CDMM block is platform specific, then
instead of just returning a zero-address, lets make the default CDMM
base address search method (mips_cdmm_phys_base()) to do something
useful. For instance to find the address in a dedicated dtb-node in
order to support of-based platforms by default.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>

---

Changelog prev:
- Use alphabetical order for the include pre-processor operator.
---
 drivers/bus/mips_cdmm.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/bus/mips_cdmm.c b/drivers/bus/mips_cdmm.c
index 1b14256376d2..9f7ed1fcd428 100644
--- a/drivers/bus/mips_cdmm.c
+++ b/drivers/bus/mips_cdmm.c
@@ -13,6 +13,8 @@
 #include <linux/cpu.h>
 #include <linux/cpumask.h>
 #include <linux/io.h>
+#include <linux/of_address.h>
+#include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 #include <linux/smp.h>
@@ -337,9 +339,22 @@ static phys_addr_t mips_cdmm_cur_base(void)
  * Picking a suitable physical address at which to map the CDMM region is
  * platform specific, so this weak function can be overridden by platform
  * code to pick a suitable value if none is configured by the bootloader.
+ * By default this method tries to find a CDMM-specific node in the system
+ * dtb. Note that this won't work for early serial console.
  */
 phys_addr_t __weak mips_cdmm_phys_base(void)
 {
+	struct device_node *np;
+	struct resource res;
+	int err;
+
+	np = of_find_compatible_node(NULL, NULL, "mti,mips-cdmm");
+	if (np) {
+		err = of_address_to_resource(np, 0, &res);
+		if (!err)
+			return res.start;
+	}
+
 	return 0;
 }
 
-- 
2.26.2

[PATCH v2 5/6] bus: cdmm: Add MIPS R5 arch support

[Serge Semin]

CDMM may be available not only on MIPS R2 architectures, but also on
newer MIPS R5 chips. For instance our P5600 chip has one. Let's mark
the CDMM bus being supported for that MIPS arch too.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---
 drivers/bus/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
index 6d4e4497b59b..971c07bc92d4 100644
--- a/drivers/bus/Kconfig
+++ b/drivers/bus/Kconfig
@@ -58,7 +58,7 @@ config IMX_WEIM
 
 config MIPS_CDMM
 	bool "MIPS Common Device Memory Map (CDMM) Driver"
-	depends on CPU_MIPSR2
+	depends on CPU_MIPSR2 || CPU_MIPSR5
 	help
 	  Driver needed for the MIPS Common Device Memory Map bus in MIPS
 	  cores. This bus is for per-CPU tightly coupled devices such as the
-- 
2.26.2

[PATCH v2 6/6] MAINTAINERS: Add maintainers for MIPS core drivers

[Serge Semin]

Add myself as a maintainer of MIPS CPU and GIC IRQchip, MIPS GIC timer
and MIPS CPS CPUidle drivers.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
---
 MAINTAINERS | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 2926327e4976..f21e51c4a0d5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11278,6 +11278,16 @@ F:	arch/mips/configs/generic/board-boston.config
 F:	drivers/clk/imgtec/clk-boston.c
 F:	include/dt-bindings/clock/boston-clock.h
 
+MIPS CORE DRIVERS
+M:	Serge Semin <fancer.lancer@gmail.com>
+L:	linux-mips@vger.kernel.org
+S:	Supported
+F:	drivers/bus/mips_cdmm.c
+F:	drivers/irqchip/irq-mips-cpu.c
+F:	drivers/irqchip/irq-mips-gic.c
+F:	drivers/clocksource/mips-gic-timer.c
+F:	drivers/cpuidle/cpuidle-cps.c
+
 MIPS GENERIC PLATFORM
 M:	Paul Burton <paulburton@kernel.org>
 L:	linux-mips@vger.kernel.org
-- 
2.26.2

Re: [PATCH RESEND v2 0/6] mips: Add DT bindings for MIPS CDMM and MIPS GIC

[Marc Zyngier]

On 2020-06-01 13:21, Serge Semin wrote:

[...]

> Since Paul isn't looking after the MIPS arch code anymore, Ralf hasn't
> been seen maintaining MIPS for a long time, Thomas is only responsible
> for the next part of it:
> 	F:      Documentation/devicetree/bindings/mips/
> 	F:      Documentation/mips/
> 	F:      arch/mips/
> 	F:      drivers/platform/mips/
> the MIPS-specific drivers like:
> 	F:	drivers/bus/mips_cdmm.c
> 	F:	drivers/irqchip/irq-mips-cpu.c
> 	F:	drivers/irqchip/irq-mips-gic.c
> 	F:	drivers/clocksource/mips-gic-timer.c
> 	F:	drivers/cpuidle/cpuidle-cps.c
> seem to be left for the subsystems maintainers to support. So if you 
> don't
> mind or unless there is a better alternative, I can help with looking
> after them to ease the maintainers review burden and since I'll be 
> working
> on our MIPS-based SoC drivers integrating into the mainline kernel repo
> anyway. If you don't like this idea, please just decline the last
> patch in the series.

Given how deeply integrated the MIPS GIC is in the architecture, I'd
really like Thomas to co-maintain it, or at the very least give his
blessing on you being the dedicated point of contact for MIPS GIC
stuff.

Thanks,

         M.
-- 
Jazz is not dead. It just smells funny...

Re: [PATCH v2 6/6] MAINTAINERS: Add maintainers for MIPS core drivers

[Andy Shevchenko]

On Mon, Jun 1, 2020 at 3:26 PM Serge Semin
<Sergey.Semin@baikalelectronics.ru> wrote:
>
> Add myself as a maintainer of MIPS CPU and GIC IRQchip, MIPS GIC timer
> and MIPS CPS CPUidle drivers.
...
> +MIPS CORE DRIVERS
> +M:     Serge Semin <fancer.lancer@gmail.com>
> +L:     linux-mips@vger.kernel.org
> +S:     Supported
> +F:     drivers/bus/mips_cdmm.c
> +F:     drivers/irqchip/irq-mips-cpu.c
> +F:     drivers/irqchip/irq-mips-gic.c
> +F:     drivers/clocksource/mips-gic-timer.c
> +F:     drivers/cpuidle/cpuidle-cps.c

I think nowadays checkpatch.pl warns on wrong ordering in this data base.


-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH v2 6/6] MAINTAINERS: Add maintainers for MIPS core drivers

[Serge Semin]

On Mon, Jun 01, 2020 at 04:56:21PM +0300, Andy Shevchenko wrote:
> On Mon, Jun 1, 2020 at 3:26 PM Serge Semin
> <Sergey.Semin@baikalelectronics.ru> wrote:
> >
> > Add myself as a maintainer of MIPS CPU and GIC IRQchip, MIPS GIC timer
> > and MIPS CPS CPUidle drivers.
> ...
> > +MIPS CORE DRIVERS
> > +M:     Serge Semin <fancer.lancer@gmail.com>
> > +L:     linux-mips@vger.kernel.org
> > +S:     Supported
> > +F:     drivers/bus/mips_cdmm.c
> > +F:     drivers/irqchip/irq-mips-cpu.c
> > +F:     drivers/irqchip/irq-mips-gic.c
> > +F:     drivers/clocksource/mips-gic-timer.c
> > +F:     drivers/cpuidle/cpuidle-cps.c
> 
> I think nowadays checkpatch.pl warns on wrong ordering in this data base.

Alas it doesn't. Good point though.

-Sergey

> 
> 
> -- 
> With Best Regards,
> Andy Shevchenko

Re: [PATCH RESEND v2 0/6] mips: Add DT bindings for MIPS CDMM and MIPS GIC

[Serge Semin]

Hello Marc,

On Mon, Jun 01, 2020 at 01:31:27PM +0100, Marc Zyngier wrote:
> On 2020-06-01 13:21, Serge Semin wrote:
> 
> [...]
> 
> > Since Paul isn't looking after the MIPS arch code anymore, Ralf hasn't
> > been seen maintaining MIPS for a long time, Thomas is only responsible
> > for the next part of it:
> > 	F:      Documentation/devicetree/bindings/mips/
> > 	F:      Documentation/mips/
> > 	F:      arch/mips/
> > 	F:      drivers/platform/mips/
> > the MIPS-specific drivers like:
> > 	F:	drivers/bus/mips_cdmm.c
> > 	F:	drivers/irqchip/irq-mips-cpu.c
> > 	F:	drivers/irqchip/irq-mips-gic.c
> > 	F:	drivers/clocksource/mips-gic-timer.c
> > 	F:	drivers/cpuidle/cpuidle-cps.c
> > seem to be left for the subsystems maintainers to support. So if you
> > don't
> > mind or unless there is a better alternative, I can help with looking
> > after them to ease the maintainers review burden and since I'll be
> > working
> > on our MIPS-based SoC drivers integrating into the mainline kernel repo
> > anyway. If you don't like this idea, please just decline the last
> > patch in the series.
> 

> Given how deeply integrated the MIPS GIC is in the architecture, I'd
> really like Thomas to co-maintain it, or at the very least give his
> blessing on you being the dedicated point of contact for MIPS GIC
> stuff.

I don't mind either way. First option might be even better. Thomas, what do you
think?

-Sergey

> 
> Thanks,
> 
>         M.
> -- 
> Jazz is not dead. It just smells funny...

Re: [PATCH v2 6/6] MAINTAINERS: Add maintainers for MIPS core drivers

[Andy Shevchenko]

On Mon, Jun 1, 2020 at 6:19 PM Serge Semin
<Sergey.Semin@baikalelectronics.ru> wrote:
> On Mon, Jun 01, 2020 at 04:56:21PM +0300, Andy Shevchenko wrote:
> > On Mon, Jun 1, 2020 at 3:26 PM Serge Semin
> > <Sergey.Semin@baikalelectronics.ru> wrote:
> > >
> > > Add myself as a maintainer of MIPS CPU and GIC IRQchip, MIPS GIC timer
> > > and MIPS CPS CPUidle drivers.
> > ...
> > > +MIPS CORE DRIVERS
> > > +M:     Serge Semin <fancer.lancer@gmail.com>
> > > +L:     linux-mips@vger.kernel.org
> > > +S:     Supported
> > > +F:     drivers/bus/mips_cdmm.c
> > > +F:     drivers/irqchip/irq-mips-cpu.c
> > > +F:     drivers/irqchip/irq-mips-gic.c
> > > +F:     drivers/clocksource/mips-gic-timer.c
> > > +F:     drivers/cpuidle/cpuidle-cps.c
> >
> > I think nowadays checkpatch.pl warns on wrong ordering in this data base.
>
> Alas it doesn't.

Ah, it definitely will.
it was relatively recently added by:
commit 9bbce40a4f72fe01a65669aee9f4036baa7fa26e
Author: Joe Perches <joe@perches.com>
Date:   Tue May 26 10:36:34 2020 +1000

   checkpatch: additional MAINTAINER section entry ordering checks


> Good point though.

You're welcome.

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH v2 6/6] MAINTAINERS: Add maintainers for MIPS core drivers

[Serge Semin]

On Mon, Jun 01, 2020 at 06:30:22PM +0300, Andy Shevchenko wrote:
> On Mon, Jun 1, 2020 at 6:19 PM Serge Semin
> <Sergey.Semin@baikalelectronics.ru> wrote:
> > On Mon, Jun 01, 2020 at 04:56:21PM +0300, Andy Shevchenko wrote:
> > > On Mon, Jun 1, 2020 at 3:26 PM Serge Semin
> > > <Sergey.Semin@baikalelectronics.ru> wrote:
> > > >
> > > > Add myself as a maintainer of MIPS CPU and GIC IRQchip, MIPS GIC timer
> > > > and MIPS CPS CPUidle drivers.
> > > ...
> > > > +MIPS CORE DRIVERS
> > > > +M:     Serge Semin <fancer.lancer@gmail.com>
> > > > +L:     linux-mips@vger.kernel.org
> > > > +S:     Supported
> > > > +F:     drivers/bus/mips_cdmm.c
> > > > +F:     drivers/irqchip/irq-mips-cpu.c
> > > > +F:     drivers/irqchip/irq-mips-gic.c
> > > > +F:     drivers/clocksource/mips-gic-timer.c
> > > > +F:     drivers/cpuidle/cpuidle-cps.c
> > >
> > > I think nowadays checkpatch.pl warns on wrong ordering in this data base.
> >
> > Alas it doesn't.
> 

> Ah, it definitely will.
> it was relatively recently added by:
> commit 9bbce40a4f72fe01a65669aee9f4036baa7fa26e
> Author: Joe Perches <joe@perches.com>
> Date:   Tue May 26 10:36:34 2020 +1000
> 
>    checkpatch: additional MAINTAINER section entry ordering checks
> 
> 
> > Good point though.
> 
> You're welcome.

Next time I won't forget that then. BTW the notes at the top of the MAINTAINERS
file don't explicitly say about the files-list order. Only about the
whole maintainers list entries order. Seeing the rest of the sub-entries like
L:, M:, etc. aren't ordered then it's probably better to have an explicit
statement, that files should be alphabetically listed, especially when
checkpatch.pl starts warning about that.

-Sergey

> 
> -- 
> With Best Regards,
> Andy Shevchenko

Re: [PATCH v2 6/6] MAINTAINERS: Add maintainers for MIPS core drivers

[Andy Shevchenko]

On Mon, Jun 1, 2020 at 6:52 PM Serge Semin
<Sergey.Semin@baikalelectronics.ru> wrote:
> On Mon, Jun 01, 2020 at 06:30:22PM +0300, Andy Shevchenko wrote:
> > On Mon, Jun 1, 2020 at 6:19 PM Serge Semin
> > <Sergey.Semin@baikalelectronics.ru> wrote:
> > > On Mon, Jun 01, 2020 at 04:56:21PM +0300, Andy Shevchenko wrote:
> > > > On Mon, Jun 1, 2020 at 3:26 PM Serge Semin
> > > > <Sergey.Semin@baikalelectronics.ru> wrote:
> > > > >
> > > > > Add myself as a maintainer of MIPS CPU and GIC IRQchip, MIPS GIC timer
> > > > > and MIPS CPS CPUidle drivers.
> > > > ...
> > > > > +MIPS CORE DRIVERS
> > > > > +M:     Serge Semin <fancer.lancer@gmail.com>
> > > > > +L:     linux-mips@vger.kernel.org
> > > > > +S:     Supported
> > > > > +F:     drivers/bus/mips_cdmm.c
> > > > > +F:     drivers/irqchip/irq-mips-cpu.c
> > > > > +F:     drivers/irqchip/irq-mips-gic.c
> > > > > +F:     drivers/clocksource/mips-gic-timer.c
> > > > > +F:     drivers/cpuidle/cpuidle-cps.c
> > > >
> > > > I think nowadays checkpatch.pl warns on wrong ordering in this data base.
> > >
> > > Alas it doesn't.
> >
>
> > Ah, it definitely will.
> > it was relatively recently added by:
> > commit 9bbce40a4f72fe01a65669aee9f4036baa7fa26e
> > Author: Joe Perches <joe@perches.com>
> > Date:   Tue May 26 10:36:34 2020 +1000
> >
> >    checkpatch: additional MAINTAINER section entry ordering checks
> >
> >
> > > Good point though.
> >
> > You're welcome.
>
> Next time I won't forget that then. BTW the notes at the top of the MAINTAINERS
> file don't explicitly say about the files-list order. Only about the
> whole maintainers list entries order. Seeing the rest of the sub-entries like
> L:, M:, etc. aren't ordered then it's probably better to have an explicit
> statement, that files should be alphabetically listed, especially when
> checkpatch.pl starts warning about that.

Joe, what do you think?

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH RESEND v2 0/6] mips: Add DT bindings for MIPS CDMM and MIPS GIC

[Thomas Bogendoerfer]

On Mon, Jun 01, 2020 at 06:24:49PM +0300, Serge Semin wrote:
> Hello Marc,
> 
> On Mon, Jun 01, 2020 at 01:31:27PM +0100, Marc Zyngier wrote:
> > On 2020-06-01 13:21, Serge Semin wrote:
> > 
> > [...]
> > 
> > > Since Paul isn't looking after the MIPS arch code anymore, Ralf hasn't
> > > been seen maintaining MIPS for a long time, Thomas is only responsible
> > > for the next part of it:
> > > 	F:      Documentation/devicetree/bindings/mips/
> > > 	F:      Documentation/mips/
> > > 	F:      arch/mips/
> > > 	F:      drivers/platform/mips/
> > > the MIPS-specific drivers like:
> > > 	F:	drivers/bus/mips_cdmm.c
> > > 	F:	drivers/irqchip/irq-mips-cpu.c
> > > 	F:	drivers/irqchip/irq-mips-gic.c
> > > 	F:	drivers/clocksource/mips-gic-timer.c
> > > 	F:	drivers/cpuidle/cpuidle-cps.c
> > > seem to be left for the subsystems maintainers to support. So if you
> > > don't
> > > mind or unless there is a better alternative, I can help with looking
> > > after them to ease the maintainers review burden and since I'll be
> > > working
> > > on our MIPS-based SoC drivers integrating into the mainline kernel repo
> > > anyway. If you don't like this idea, please just decline the last
> > > patch in the series.
> > 
> 
> > Given how deeply integrated the MIPS GIC is in the architecture, I'd
> > really like Thomas to co-maintain it, or at the very least give his
> > blessing on you being the dedicated point of contact for MIPS GIC
> > stuff.
> 
> I don't mind either way. First option might be even better. Thomas,
> what do you think?

sure, I'm happy to be your co-maintainer.

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]

Re: [PATCH RESEND v2 0/6] mips: Add DT bindings for MIPS CDMM and MIPS GIC

[Serge Semin]

On Mon, Jun 01, 2020 at 06:56:46PM +0200, Thomas Bogendoerfer wrote:
> On Mon, Jun 01, 2020 at 06:24:49PM +0300, Serge Semin wrote:
> > Hello Marc,
> > 
> > On Mon, Jun 01, 2020 at 01:31:27PM +0100, Marc Zyngier wrote:
> > > On 2020-06-01 13:21, Serge Semin wrote:
> > > 
> > > [...]
> > > 
> > > > Since Paul isn't looking after the MIPS arch code anymore, Ralf hasn't
> > > > been seen maintaining MIPS for a long time, Thomas is only responsible
> > > > for the next part of it:
> > > > 	F:      Documentation/devicetree/bindings/mips/
> > > > 	F:      Documentation/mips/
> > > > 	F:      arch/mips/
> > > > 	F:      drivers/platform/mips/
> > > > the MIPS-specific drivers like:
> > > > 	F:	drivers/bus/mips_cdmm.c
> > > > 	F:	drivers/irqchip/irq-mips-cpu.c
> > > > 	F:	drivers/irqchip/irq-mips-gic.c
> > > > 	F:	drivers/clocksource/mips-gic-timer.c
> > > > 	F:	drivers/cpuidle/cpuidle-cps.c
> > > > seem to be left for the subsystems maintainers to support. So if you
> > > > don't
> > > > mind or unless there is a better alternative, I can help with looking
> > > > after them to ease the maintainers review burden and since I'll be
> > > > working
> > > > on our MIPS-based SoC drivers integrating into the mainline kernel repo
> > > > anyway. If you don't like this idea, please just decline the last
> > > > patch in the series.
> > > 
> > 
> > > Given how deeply integrated the MIPS GIC is in the architecture, I'd
> > > really like Thomas to co-maintain it, or at the very least give his
> > > blessing on you being the dedicated point of contact for MIPS GIC
> > > stuff.
> > 
> > I don't mind either way. First option might be even better. Thomas,
> > what do you think?
> 
> sure, I'm happy to be your co-maintainer.
> 

Great! As soon as we finish a discussion regarding the files-list ordering
raised around the last patch in the series, I'll resend the patchset with you
added to the list of the MIPS core drivers maintainers.

-Sergey

> Thomas.
> 
> -- 
> Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
> good idea.                                                [ RFC1925, 2.3 ]

[RFC PATCH -next] MAINTAINERS: Update F: and X: entry ordering (was Re: [PATCH v2 6/6] MAINTAINERS: Add maintainers for MIPS core drivers)

[Joe Perches]

On Mon, 2020-06-01 at 19:04 +0300, Andy Shevchenko wrote:
> On Mon, Jun 1, 2020 at 6:52 PM Serge Semin <Sergey.Semin@baikalelectronics.ru> wrote:
> > On Mon, Jun 01, 2020 at 06:30:22PM +0300, Andy Shevchenko wrote:
> > > On Mon, Jun 1, 2020 at 6:19 PM Serge Semin <Sergey.Semin@baikalelectronics.ru> wrote:
> > > > On Mon, Jun 01, 2020 at 04:56:21PM +0300, Andy Shevchenko wrote:
> > > > > On Mon, Jun 1, 2020 at 3:26 PM Serge Semin <Sergey.Semin@baikalelectronics.ru> wrote:
> > > > > > Add myself as a maintainer of MIPS CPU and GIC IRQchip, MIPS GIC timer
> > > > > > and MIPS CPS CPUidle drivers.
> > > > > ...
> > > > > > +MIPS CORE DRIVERS
> > > > > > +M:     Serge Semin <fancer.lancer@gmail.com>
> > > > > > +L:     linux-mips@vger.kernel.org
> > > > > > +S:     Supported
> > > > > > +F:     drivers/bus/mips_cdmm.c
> > > > > > +F:     drivers/irqchip/irq-mips-cpu.c
> > > > > > +F:     drivers/irqchip/irq-mips-gic.c
> > > > > > +F:     drivers/clocksource/mips-gic-timer.c
> > > > > > +F:     drivers/cpuidle/cpuidle-cps.c
> > > > > 
> > > > > I think nowadays checkpatch.pl warns on wrong ordering in this data base.
[]
> > Next time I won't forget that then. BTW the notes at the top of the MAINTAINERS
> > file don't explicitly say about the files-list order. Only about the
> > whole maintainers list entries order. Seeing the rest of the sub-entries like
> > L:, M:, etc. aren't ordered then it's probably better to have an explicit
> > statement, that files should be alphabetically listed, especially when
> > checkpatch.pl starts warning about that.
> 
> Joe, what do you think?

Fine by me.  Maybe something like the below.

Another thing might be to intermix the F and X entries so that
exclusions are more obviously against the F: entries.

There aren't many MAINTAINERS lines changed when the modified
parse-maintainers is run, but I think it reads better.

It doesn't seem the last major reordering with parse-maintainers
caused any significant issue for anyone.

I think having Linus run scripts/parse-maintainers.pl just before
every release or every few releases would make this issue go away.
---
 MAINTAINERS                  |  1 +
 scripts/checkpatch.pl        | 17 +++++++----------
 scripts/parse-maintainers.pl |  5 ++---
 3 files changed, 10 insertions(+), 13 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index b045b70e54df..4b53119504ff 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -118,6 +118,7 @@ Descriptions of section entries and preferred order
 	   F:	net/
 	   X:	net/ipv6/
 	   matches all files in and below net excluding net/ipv6/
+	   F: and X: entries are intermixed in case sensitive alphabetic order
 	N: Files and directories *Regex* patterns.
 	   N:	[^a-z]tegra	all files whose path contains tegra
 	                        (not including files like integrator)
diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
index dd750241958b..499c85be0b2f 100755
--- a/scripts/checkpatch.pl
+++ b/scripts/checkpatch.pl
@@ -3099,16 +3099,13 @@ sub process {
 				if ($curindex < 0) {
 					WARN("MAINTAINERS_STYLE",
 					     "Unknown MAINTAINERS entry type: '$cur'\n" . $herecurr);
-				} else {
-					if ($previndex >= 0 && $curindex < $previndex) {
-						WARN("MAINTAINERS_STYLE",
-						     "Misordered MAINTAINERS entry - list '$cur:' before '$prev:'\n" . $hereprev);
-					} elsif ((($prev eq 'F' && $cur eq 'F') ||
-						  ($prev eq 'X' && $cur eq 'X')) &&
-						 ($prevval cmp $curval) > 0) {
-						WARN("MAINTAINERS_STYLE",
-						     "Misordered MAINTAINERS entry - list file patterns in alphabetic order\n" . $hereprev);
-					}
+				} elsif ($previndex >= 0 && $curindex < $previndex && !($prev =~ /[FX]/ && $cur =~ /[FX]/)) {
+					WARN("MAINTAINERS_STYLE",
+					     "Misordered MAINTAINERS entry - list '$cur:' before '$prev:'\n" . $hereprev);
+				} elsif ((($prev =~ /[FX]/ && $cur =~ /[FX]/) &&
+					  ($prevval cmp $curval) > 0)) {
+					WARN("MAINTAINERS_STYLE",
+					     "Misordered MAINTAINERS entry - list F and X file patterns in alphabetic order\n" . $hereprev);
 				}
 			}
 		}
diff --git a/scripts/parse-maintainers.pl b/scripts/parse-maintainers.pl
index 2ca4eb3f190d..8d2247a596f0 100755
--- a/scripts/parse-maintainers.pl
+++ b/scripts/parse-maintainers.pl
@@ -84,9 +84,8 @@ sub by_pattern($$) {
     $a_index = 1000 if ($a_index == -1);
     $b_index = 1000 if ($b_index == -1);
 
-    if (($a1 =~ /^F$/ && $b1 =~ /^F$/) ||
-	($a1 =~ /^X$/ && $b1 =~ /^X$/)) {
-	return $a cmp $b;
+    if (($a1 =~ /^[FX]$/ && $b1 =~ /^[FX]$/)) {
+	return substr($a, 1) cmp substr($b, 1);
     }
 
     if ($a_index < $b_index) {

Re: [RFC PATCH -next] MAINTAINERS: Update F: and X: entry ordering (was Re: [PATCH v2 6/6] MAINTAINERS: Add maintainers for MIPS core drivers)

[Serge Semin]

Hello Joe

On Mon, Jun 01, 2020 at 11:22:58AM -0700, Joe Perches wrote:
> On Mon, 2020-06-01 at 19:04 +0300, Andy Shevchenko wrote:
> > On Mon, Jun 1, 2020 at 6:52 PM Serge Semin <Sergey.Semin@baikalelectronics.ru> wrote:
> > > On Mon, Jun 01, 2020 at 06:30:22PM +0300, Andy Shevchenko wrote:
> > > > On Mon, Jun 1, 2020 at 6:19 PM Serge Semin <Sergey.Semin@baikalelectronics.ru> wrote:
> > > > > On Mon, Jun 01, 2020 at 04:56:21PM +0300, Andy Shevchenko wrote:
> > > > > > On Mon, Jun 1, 2020 at 3:26 PM Serge Semin <Sergey.Semin@baikalelectronics.ru> wrote:
> > > > > > > Add myself as a maintainer of MIPS CPU and GIC IRQchip, MIPS GIC timer
> > > > > > > and MIPS CPS CPUidle drivers.
> > > > > > ...
> > > > > > > +MIPS CORE DRIVERS
> > > > > > > +M:     Serge Semin <fancer.lancer@gmail.com>
> > > > > > > +L:     linux-mips@vger.kernel.org
> > > > > > > +S:     Supported
> > > > > > > +F:     drivers/bus/mips_cdmm.c
> > > > > > > +F:     drivers/irqchip/irq-mips-cpu.c
> > > > > > > +F:     drivers/irqchip/irq-mips-gic.c
> > > > > > > +F:     drivers/clocksource/mips-gic-timer.c
> > > > > > > +F:     drivers/cpuidle/cpuidle-cps.c
> > > > > > 
> > > > > > I think nowadays checkpatch.pl warns on wrong ordering in this data base.
> []
> > > Next time I won't forget that then. BTW the notes at the top of the MAINTAINERS
> > > file don't explicitly say about the files-list order. Only about the
> > > whole maintainers list entries order. Seeing the rest of the sub-entries like
> > > L:, M:, etc. aren't ordered then it's probably better to have an explicit
> > > statement, that files should be alphabetically listed, especially when
> > > checkpatch.pl starts warning about that.
> > 
> > Joe, what do you think?
> 
> Fine by me.  Maybe something like the below.
> 
> Another thing might be to intermix the F and X entries so that
> exclusions are more obviously against the F: entries.
> 
> There aren't many MAINTAINERS lines changed when the modified
> parse-maintainers is run, but I think it reads better.
> 
> It doesn't seem the last major reordering with parse-maintainers
> caused any significant issue for anyone.

I was also thinking about a text explaining the F: section order requirement.
Like this:

diff --git a/MAINTAINERS b/MAINTAINERS
index 865aeafee3b2..253f8f97891f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -111,7 +111,8 @@ Descriptions of section entries and preferred order
 	   F:	drivers/net/	all files in and below drivers/net
 	   F:	drivers/net/*	all files in drivers/net, but not below
 	   F:	*/net/*		all files in "any top level directory"/net
-	   One pattern per line.  Multiple F: lines acceptable.
+	   One pattern per line. Multiple F: lines acceptable, but are
+	   supposed to be listed in alphabetical order.
 	X: *Excluded* files and directories that are NOT maintained, same
 	   rules as F:. Files exclusions are tested before file matches.
 	   Can be useful for excluding a specific subdirectory, for instance:

The rest suggested by you is fine with me. Intermixing F and X seems reasonable
so the maintainers could group inclusion and exclusion sections together
with respect to the files/directories they refer to.

-Sergey

> 
> I think having Linus run scripts/parse-maintainers.pl just before
> every release or every few releases would make this issue go away.
> ---
>  MAINTAINERS                  |  1 +
>  scripts/checkpatch.pl        | 17 +++++++----------
>  scripts/parse-maintainers.pl |  5 ++---
>  3 files changed, 10 insertions(+), 13 deletions(-)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index b045b70e54df..4b53119504ff 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -118,6 +118,7 @@ Descriptions of section entries and preferred order
>  	   F:	net/
>  	   X:	net/ipv6/
>  	   matches all files in and below net excluding net/ipv6/
> +	   F: and X: entries are intermixed in case sensitive alphabetic order
>  	N: Files and directories *Regex* patterns.
>  	   N:	[^a-z]tegra	all files whose path contains tegra
>  	                        (not including files like integrator)
> diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
> index dd750241958b..499c85be0b2f 100755
> --- a/scripts/checkpatch.pl
> +++ b/scripts/checkpatch.pl
> @@ -3099,16 +3099,13 @@ sub process {
>  				if ($curindex < 0) {
>  					WARN("MAINTAINERS_STYLE",
>  					     "Unknown MAINTAINERS entry type: '$cur'\n" . $herecurr);
> -				} else {
> -					if ($previndex >= 0 && $curindex < $previndex) {
> -						WARN("MAINTAINERS_STYLE",
> -						     "Misordered MAINTAINERS entry - list '$cur:' before '$prev:'\n" . $hereprev);
> -					} elsif ((($prev eq 'F' && $cur eq 'F') ||
> -						  ($prev eq 'X' && $cur eq 'X')) &&
> -						 ($prevval cmp $curval) > 0) {
> -						WARN("MAINTAINERS_STYLE",
> -						     "Misordered MAINTAINERS entry - list file patterns in alphabetic order\n" . $hereprev);
> -					}
> +				} elsif ($previndex >= 0 && $curindex < $previndex && !($prev =~ /[FX]/ && $cur =~ /[FX]/)) {
> +					WARN("MAINTAINERS_STYLE",
> +					     "Misordered MAINTAINERS entry - list '$cur:' before '$prev:'\n" . $hereprev);
> +				} elsif ((($prev =~ /[FX]/ && $cur =~ /[FX]/) &&
> +					  ($prevval cmp $curval) > 0)) {
> +					WARN("MAINTAINERS_STYLE",
> +					     "Misordered MAINTAINERS entry - list F and X file patterns in alphabetic order\n" . $hereprev);
>  				}
>  			}
>  		}
> diff --git a/scripts/parse-maintainers.pl b/scripts/parse-maintainers.pl
> index 2ca4eb3f190d..8d2247a596f0 100755
> --- a/scripts/parse-maintainers.pl
> +++ b/scripts/parse-maintainers.pl
> @@ -84,9 +84,8 @@ sub by_pattern($$) {
>      $a_index = 1000 if ($a_index == -1);
>      $b_index = 1000 if ($b_index == -1);
>  
> -    if (($a1 =~ /^F$/ && $b1 =~ /^F$/) ||
> -	($a1 =~ /^X$/ && $b1 =~ /^X$/)) {
> -	return $a cmp $b;
> +    if (($a1 =~ /^[FX]$/ && $b1 =~ /^[FX]$/)) {
> +	return substr($a, 1) cmp substr($b, 1);
>      }
>  
>      if ($a_index < $b_index) {
> 
>