From: Marek Behun <marek.behun@nic.cz>
To: Jonathan McDowell <noodles@earth.li>
Cc: Andrew Lunn <andrew@lunn.ch>,
Vivien Didelot <vivien.didelot@gmail.com>,
Florian Fainelli <f.fainelli@gmail.com>,
"David S. Miller" <davem@davemloft.net>,
Jakub Kicinski <kuba@kernel.org>,
netdev@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/2] net: dsa: qca8k: introduce SGMII configuration options
Date: Fri, 5 Jun 2020 20:28:04 +0200 [thread overview]
Message-ID: <20200605202804.1dd78ee8@nic.cz> (raw)
In-Reply-To: <8ddd76e484e1bedd12c87ea0810826b60e004a65.1591380105.git.noodles@earth.li>
On Fri, 5 Jun 2020 19:10:58 +0100
Jonathan McDowell <noodles@earth.li> wrote:
> The QCA8337(N) has an SGMII port which can operate in MAC, PHY or BASE-X
> mode depending on what it's connected to (e.g. CPU vs external PHY or
> SFP). At present the driver does no configuration of this port even if
> it is selected.
>
> Add support for making sure the SGMII is enabled if it's in use, and
> device tree support for configuring the connection details.
>
> Signed-off-by: Jonathan McDowell <noodles@earth.li>
> ---
> drivers/net/dsa/qca8k.c | 44 ++++++++++++++++++++++++++++++++++++++++-
> drivers/net/dsa/qca8k.h | 12 +++++++++++
> 2 files changed, 55 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c
> index 9f4205b4439b..5b7979aca9b9 100644
> --- a/drivers/net/dsa/qca8k.c
> +++ b/drivers/net/dsa/qca8k.c
> @@ -418,6 +418,40 @@ qca8k_mib_init(struct qca8k_priv *priv)
> mutex_unlock(&priv->reg_mutex);
> }
>
> +static int
> +qca8k_setup_sgmii(struct qca8k_priv *priv)
> +{
> + const char *mode;
> + u32 val;
> +
> + val = qca8k_read(priv, QCA8K_REG_SGMII_CTRL);
> +
> + val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |
> + QCA8K_SGMII_EN_TX | QCA8K_SGMII_EN_SD;
> +
> + if (of_property_read_bool(priv->dev->of_node, "sgmii-delay"))
> + val |= QCA8K_SGMII_CLK125M_DELAY;
> +
> + if (of_property_read_string(priv->dev->of_node, "sgmii-mode", &mode)) {
> + val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
> +
> + if (!strcasecmp(mode, "basex")) {
> + val |= QCA8K_SGMII_MODE_CTRL_BASEX;
> + } else if (!strcasecmp(mode, "mac")) {
> + val |= QCA8K_SGMII_MODE_CTRL_MAC;
> + } else if (!strcasecmp(mode, "phy")) {
> + val |= QCA8K_SGMII_MODE_CTRL_PHY;
> + } else {
> + pr_err("Unrecognised SGMII mode %s\n", mode);
> + return -EINVAL;
> + }
> + }
There is no sgmii-mode device tree property documented. You should
infere this settings from the existing device tree bindings, ie look at
phy-mode. You can use of_get_phy_mode function, or something from
of_mdio.c, or better yet change the api in this driver to use the new
phylink API.
Marek
> +
> + qca8k_write(priv, QCA8K_REG_SGMII_CTRL, val);
> +
> + return 0;
> +}
> +
> static int
> qca8k_set_pad_ctrl(struct qca8k_priv *priv, int port, int mode)
> {
> @@ -458,7 +492,8 @@ qca8k_set_pad_ctrl(struct qca8k_priv *priv, int port, int mode)
> break;
> case PHY_INTERFACE_MODE_SGMII:
> qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);
> - break;
> +
> + return qca8k_setup_sgmii(priv);
> default:
> pr_err("xMII mode %d not supported\n", mode);
> return -EINVAL;
> @@ -661,6 +696,13 @@ qca8k_setup(struct dsa_switch *ds)
> if (ret)
> return ret;
>
> + if (of_property_read_bool(priv->dev->of_node,
> + "disable-serdes-autoneg")) {
> + mask = qca8k_read(priv, QCA8K_REG_PWS) |
> + QCA8K_PWS_SERDES_AEN_DIS;
> + qca8k_write(priv, QCA8K_REG_PWS, mask);
> + }
> +
> /* Initialize CPU port pad mode (xMII type, delays...) */
> ret = of_get_phy_mode(dsa_to_port(ds, QCA8K_CPU_PORT)->dn, &phy_mode);
> if (ret) {
> diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h
> index 42d6ea24eb14..cd97c212f3f8 100644
> --- a/drivers/net/dsa/qca8k.h
> +++ b/drivers/net/dsa/qca8k.h
> @@ -36,6 +36,8 @@
> #define QCA8K_MAX_DELAY 3
> #define QCA8K_PORT_PAD_RGMII_RX_DELAY_EN BIT(24)
> #define QCA8K_PORT_PAD_SGMII_EN BIT(7)
> +#define QCA8K_REG_PWS 0x010
> +#define QCA8K_PWS_SERDES_AEN_DIS BIT(7)
> #define QCA8K_REG_MODULE_EN 0x030
> #define QCA8K_MODULE_EN_MIB BIT(0)
> #define QCA8K_REG_MIB 0x034
> @@ -77,6 +79,16 @@
> #define QCA8K_PORT_HDR_CTRL_ALL 2
> #define QCA8K_PORT_HDR_CTRL_MGMT 1
> #define QCA8K_PORT_HDR_CTRL_NONE 0
> +#define QCA8K_REG_SGMII_CTRL 0x0e0
> +#define QCA8K_SGMII_EN_PLL BIT(1)
> +#define QCA8K_SGMII_EN_RX BIT(2)
> +#define QCA8K_SGMII_EN_TX BIT(3)
> +#define QCA8K_SGMII_EN_SD BIT(4)
> +#define QCA8K_SGMII_CLK125M_DELAY BIT(7)
> +#define QCA8K_SGMII_MODE_CTRL_MASK (BIT(22) | BIT(23))
> +#define QCA8K_SGMII_MODE_CTRL_BASEX 0
> +#define QCA8K_SGMII_MODE_CTRL_PHY BIT(22)
> +#define QCA8K_SGMII_MODE_CTRL_MAC BIT(23)
>
> /* EEE control registers */
> #define QCA8K_REG_EEE_CTRL 0x100
next prev parent reply other threads:[~2020-06-05 18:28 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-05 18:08 [PATCH 0/2] net: dsa: qca8k: Add SGMII configuration options Jonathan McDowell
2020-06-05 18:10 ` [PATCH 1/2] dt-bindings: net: dsa: qca8k: document SGMII properties Jonathan McDowell
2020-06-15 17:45 ` Rob Herring
2020-06-15 18:15 ` Jonathan McDowell
2020-06-05 18:10 ` [PATCH 2/2] net: dsa: qca8k: introduce SGMII configuration options Jonathan McDowell
2020-06-05 18:28 ` Marek Behun [this message]
2020-06-05 18:38 ` Andrew Lunn
2020-06-06 7:49 ` Jonathan McDowell
2020-06-06 8:37 ` Russell King - ARM Linux admin
2020-06-06 10:59 ` Jonathan McDowell
2020-06-06 13:43 ` Russell King - ARM Linux admin
2020-06-06 18:02 ` Jonathan McDowell
2020-06-06 14:03 ` Andrew Lunn
2020-06-08 18:39 ` [RFC PATCH v2] net: dsa: qca8k: Improve SGMII interface handling Jonathan McDowell
2020-06-08 19:10 ` Russell King - ARM Linux admin
2020-06-10 19:13 ` [RFC PATCH v3 0/2] " Jonathan McDowell
2020-06-10 19:14 ` [PATCH 1/2] net: dsa: qca8k: Switch to PHYLINK instead of PHYLIB Jonathan McDowell
2020-06-11 3:15 ` Florian Fainelli
2020-06-11 8:55 ` Russell King - ARM Linux admin
2020-06-11 9:01 ` Vladimir Oltean
2020-06-12 11:53 ` Jonathan McDowell
2020-06-11 8:58 ` Vladimir Oltean
2020-06-11 11:04 ` Jonathan McDowell
2020-06-10 19:15 ` [PATCH 2/2] net: dsa: qca8k: Improve SGMII interface handling Jonathan McDowell
2020-06-11 3:31 ` Florian Fainelli
2020-06-11 17:47 ` Jonathan McDowell
2020-06-11 8:58 ` Russell King - ARM Linux admin
2020-06-10 23:29 ` [RFC PATCH v3 0/2] " David Miller
2020-06-13 11:31 ` [RFC PATCH v4 " Jonathan McDowell
2020-06-13 11:31 ` [RFC PATCH v4 1/2] net: dsa: qca8k: Switch to PHYLINK instead of PHYLIB Jonathan McDowell
2020-06-13 19:30 ` Vladimir Oltean
2020-06-13 11:32 ` [RFC PATCH v4 2/2] net: dsa: qca8k: Improve SGMII interface handling Jonathan McDowell
2020-06-13 20:10 ` Vladimir Oltean
2020-06-14 17:20 ` Jonathan McDowell
2020-06-20 10:30 ` [PATCH net-next v5 0/3] " Jonathan McDowell
2020-06-20 10:30 ` [PATCH net-next v5 1/3] net: dsa: qca8k: Switch to PHYLINK instead of PHYLIB Jonathan McDowell
2020-06-20 10:31 ` [PATCH net-next v5 2/3] net: dsa: qca8k: Improve SGMII interface handling Jonathan McDowell
2020-06-20 10:31 ` [PATCH net-next v5 3/3] net: dsa: qca8k: Minor comment spelling fix Jonathan McDowell
2020-06-22 22:54 ` [PATCH net-next v5 0/3] net: dsa: qca8k: Improve SGMII interface handling David Miller
2020-06-19 8:12 ` [PATCH 2/2] net: dsa: qca8k: introduce SGMII configuration options Dan Carpenter
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