From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.7 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 346BAC433DF for ; Tue, 9 Jun 2020 08:08:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 132F8207C3 for ; Tue, 9 Jun 2020 08:08:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="wW9CjXs1" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728106AbgFIIIL (ORCPT ); Tue, 9 Jun 2020 04:08:11 -0400 Received: from esa2.microchip.iphmx.com ([68.232.149.84]:45986 "EHLO esa2.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726404AbgFIIIK (ORCPT ); Tue, 9 Jun 2020 04:08:10 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1591690090; x=1623226090; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=j8GXkZLUH+agWrXuo05iZ8Ra5e5w172JpXOOCnWEBk0=; b=wW9CjXs144eqyYMrLHGNWi8XKtxQ6dlZ30MwS/sCb+AjiZLTIljT0L4K lB3wU/pY84c6DWEURH/DXHzzuhGzzzIrGc3LJjmpIpWT5YBzYb3jP5FaN WwBfKzmqCCm1Gn7FZ2kv7Gz33eyNUPn0yd1nDC4auEWRXzq2ky8jt8ggy NY1TWsUXmH0LTjgSLVCu/QcN059xluEh2BJafESBKHkhJ9RiHlvRgCqrS WY1oTJtwWHmzgAsnhrkj8DX8Xbzskr22Mn8I3HXUic8W/UeRD6HRtRvJc aFHWfIATtiCMJQG6W0zzXheNDRWHrKglAl9EMrdt+Gy5wt2swdriLFkOh g==; IronPort-SDR: WIjVcXp9+x7tNl0DVjMyLtnn6Pe3z66EZw9JQ2tIEQ9l2AdQECxm9lZibNLwD59PQDb3jk3Fc5 izU3jQEwkYkf9tIgdwPukmG5GBwh3ofDbBI9qDYV+mc2L/WzHdGqVhL71bKnrhsVoXE+YorfRp 18EjHFNnBvklR3xrfI2N9p7QYzU+IETO8Eb2CP8ioqFV9+P7keZxO1fDWPALNRUbDC6mzurBMk u8pdVQ2ClK1C2K0Z/OQbjtwe4j3J3YlJMqP0Yzs/d8Bdx/vuvxZgDwr14OjA+HgKlFZ+DDZj1C GWM= X-IronPort-AV: E=Sophos;i="5.73,491,1583218800"; d="scan'208";a="77808660" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 09 Jun 2020 01:08:09 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Tue, 9 Jun 2020 01:08:08 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.1847.3 via Frontend Transport; Tue, 9 Jun 2020 01:08:06 -0700 From: Lars Povlsen To: Arnd Bergmann , Stephen Boyd , "Linus Walleij" CC: Lars Povlsen , Steen Hegelund , Microchip Linux Driver Support , Olof Johansson , "Michael Turquette" , , , , , , Alexandre Belloni Subject: [PATCH v2 04/10] arm64: dts: sparx5: Add pinctrl support Date: Tue, 9 Jun 2020 10:07:03 +0200 Message-ID: <20200609080709.9654-4-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200609080709.9654-1-lars.povlsen@microchip.com> References: <20200608123024.5330-1-lars.povlsen@microchip.com> <20200609080709.9654-1-lars.povlsen@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This add pinctrl support to the Microchip Sparx5 SoC. Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 26 +++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 4a54b7d039167..baf4176ce1dfe 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -109,6 +109,8 @@ gic: interrupt-controller@600300000 { }; uart0: serial@600100000 { + pinctrl-0 = <&uart_pins>; + pinctrl-names = "default"; compatible = "ns16550a"; reg = <0x6 0x00100000 0x20>; clocks = <&ahb_clk>; @@ -120,6 +122,8 @@ uart0: serial@600100000 { }; uart1: serial@600102000 { + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; compatible = "ns16550a"; reg = <0x6 0x00102000 0x20>; clocks = <&ahb_clk>; @@ -138,5 +142,27 @@ timer1: timer@600105000 { interrupts = ; }; + gpio: pinctrl@6110101e0 { + compatible = "microchip,sparx5-pinctrl"; + reg = <0x6 0x110101e0 0x90>, <0x6 0x10508010 0x100>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&gpio 0 0 64>; + interrupt-controller; + interrupts = ; + #interrupt-cells = <2>; + + uart_pins: uart-pins { + pins = "GPIO_10", "GPIO_11"; + function = "uart"; + }; + + uart2_pins: uart2-pins { + pins = "GPIO_26", "GPIO_27"; + function = "uart2"; + }; + + }; + }; }; -- 2.27.0