From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21B0DC433E0 for ; Wed, 10 Jun 2020 20:21:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EA9B720760 for ; Wed, 10 Jun 2020 20:21:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728129AbgFJUV5 (ORCPT ); Wed, 10 Jun 2020 16:21:57 -0400 Received: from mga18.intel.com ([134.134.136.126]:53249 "EHLO mga18.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727783AbgFJUVv (ORCPT ); Wed, 10 Jun 2020 16:21:51 -0400 IronPort-SDR: GrPLv8PZTtIDDB1GDzNZNyg2C8UNjBiKRFhP41uHf3YmyXcNrN1TX1JJfhSl1UJUyFNBfY1El0 AsNuzSBwB0kA== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jun 2020 13:21:50 -0700 IronPort-SDR: 8lcjdtOHx4dqpqZ/3uWvLYf1TFhhxR1o5go7qMZglqwrXPXTpgcGfMkJruNB5BqLyBesVLkUgW O3SU+EVnFaXQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,497,1583222400"; d="scan'208";a="380178483" Received: from km-skylake-client-platform.sc.intel.com ([10.3.52.141]) by fmsmga001.fm.intel.com with ESMTP; 10 Jun 2020 13:21:50 -0700 From: Kyung Min Park To: x86@kernel.org, linux-kernel@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, gregkh@linuxfoundation.org, ak@linux.intel.com, dave.hansen@intel.com, tony.luck@intel.com, ravi.v.shankar@intel.com, ricardo.neri@intel.com, Ricardo Neri Subject: [RFC PATCH 2/3] x86/cpufeatures: Add enumeration for SERIALIZE instruction Date: Wed, 10 Jun 2020 13:07:00 -0700 Message-Id: <20200610200701.16757-3-kyung.min.park@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200610200701.16757-1-kyung.min.park@intel.com> References: <20200610200701.16757-1-kyung.min.park@intel.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ricardo Neri This instruction gives software a way to force the processor to complete all modifications to flags, registers and memory from previous instructions and drain all buffered writes to memory before the next instruction is fetched and executed. The same effect can be obtained using the cpuid instruction. However, cpuid causes modification on the eax, ebx, ecx, and ecx regiters; it also causes a VM exit. A processor supports SERIALIZE instruction if CPUID.0x0x.0x0:EDX[14] is present. The CPU feature flag is shown as "serialize" in /proc/cpuinfo. Detailed information on the instructions and CPUID feature flag SERIALIZE can be found in the latest Intel Architecture Instruction Set Extensions and Future Features Programming Reference and Intel 64 and IA-32 Architectures Software Developer's Manual. Signed-off-by: Ricardo Neri --- arch/x86/include/asm/cpufeatures.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index db189945e9b0..cd9b1ec022ec 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -364,6 +364,7 @@ #define X86_FEATURE_AVX512_VP2INTERSECT (18*32+ 8) /* AVX-512 Intersect for D/Q */ #define X86_FEATURE_MD_CLEAR (18*32+10) /* VERW clears CPU buffers */ #define X86_FEATURE_TSX_FORCE_ABORT (18*32+13) /* "" TSX_FORCE_ABORT */ +#define X86_FEATURE_SERIALIZE (18*32+14) /* SERIALIZE instruction */ #define X86_FEATURE_PCONFIG (18*32+18) /* Intel PCONFIG */ #define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */ #define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */ -- 2.17.1