* [PATCH V3 0/2] Fix issues related to register access in IPQ NAND
@ 2020-06-12 6:49 Sivaprakash Murugesan
2020-06-12 6:49 ` [PATCH V3 1/2] mtd: rawnand: qcom: avoid write to unavailable register Sivaprakash Murugesan
2020-06-12 6:49 ` [PATCH V3 2/2] mtd: rawnand: qcom: set BAM mode only if not set already Sivaprakash Murugesan
0 siblings, 2 replies; 5+ messages in thread
From: Sivaprakash Murugesan @ 2020-06-12 6:49 UTC (permalink / raw)
To: miquel.raynal, richard, vigneshr, peter.ujfalusi, sivaprak,
boris.brezillon, architt, linux-mtd, linux-kernel
Patch 1: avoids register write to unavailable SFLASHC_BURST_CFG register
Patch 2: set BAM mode only if not set by bootloader
[V3]
* Addressed review comments from Miquel
[V2]
* As per review comments from Miquèl split the original patch into two
addressing independent issues.
Sivaprakash Murugesan (2):
mtd: rawnand: qcom: remove write to unavailable register
mtd: rawnand: qcom: set BAM mode only if not set already
drivers/mtd/nand/raw/qcom_nandc.c | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
--
2.7.4
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH V3 1/2] mtd: rawnand: qcom: avoid write to unavailable register
2020-06-12 6:49 [PATCH V3 0/2] Fix issues related to register access in IPQ NAND Sivaprakash Murugesan
@ 2020-06-12 6:49 ` Sivaprakash Murugesan
2020-06-12 7:16 ` Miquel Raynal
2020-06-12 6:49 ` [PATCH V3 2/2] mtd: rawnand: qcom: set BAM mode only if not set already Sivaprakash Murugesan
1 sibling, 1 reply; 5+ messages in thread
From: Sivaprakash Murugesan @ 2020-06-12 6:49 UTC (permalink / raw)
To: miquel.raynal, richard, vigneshr, peter.ujfalusi, sivaprak,
boris.brezillon, architt, linux-mtd, linux-kernel
Cc: stable
SFLASHC_BURST_CFG is only available on older ipq nand platforms, this
register has been removed when the NAND controller is moved as part of qpic
controller.
avoid register writes to this register on devices which are based on qpic
NAND controllers.
Fixes: a0637834 (mtd: nand: qcom: support for IPQ4019 QPIC NANDcontroller)
Fixes: dce84760 (mtd: nand: qcom: Support for IPQ8074 QPIC NAND controller)
Cc: stable@vger.kernel.org
Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
---
[V3]
* Addressed Miquel comments, added flag based on nand controller hw
to avoid the register writes to specific ipq platforms
drivers/mtd/nand/raw/qcom_nandc.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
index f1daf33..e0c55bb 100644
--- a/drivers/mtd/nand/raw/qcom_nandc.c
+++ b/drivers/mtd/nand/raw/qcom_nandc.c
@@ -459,11 +459,13 @@ struct qcom_nand_host {
* among different NAND controllers.
* @ecc_modes - ecc mode for NAND
* @is_bam - whether NAND controller is using BAM
+ * @is_qpic - whether NAND CTRL is part of qpic IP
* @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset
*/
struct qcom_nandc_props {
u32 ecc_modes;
bool is_bam;
+ bool is_qpic;
u32 dev_cmd_reg_start;
};
@@ -2774,7 +2776,8 @@ static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
u32 nand_ctrl;
/* kill onenand */
- nandc_write(nandc, SFLASHC_BURST_CFG, 0);
+ if (!nandc->props->is_qpic)
+ nandc_write(nandc, SFLASHC_BURST_CFG, 0);
nandc_write(nandc, dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD),
NAND_DEV_CMD_VLD_VAL);
@@ -3029,18 +3032,21 @@ static int qcom_nandc_remove(struct platform_device *pdev)
static const struct qcom_nandc_props ipq806x_nandc_props = {
.ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
.is_bam = false,
+ .is_qpic = false,
.dev_cmd_reg_start = 0x0,
};
static const struct qcom_nandc_props ipq4019_nandc_props = {
.ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
.is_bam = true,
+ .is_qpic = true,
.dev_cmd_reg_start = 0x0,
};
static const struct qcom_nandc_props ipq8074_nandc_props = {
.ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
.is_bam = true,
+ .is_qpic = true,
.dev_cmd_reg_start = 0x7000,
};
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH V3 2/2] mtd: rawnand: qcom: set BAM mode only if not set already
2020-06-12 6:49 [PATCH V3 0/2] Fix issues related to register access in IPQ NAND Sivaprakash Murugesan
2020-06-12 6:49 ` [PATCH V3 1/2] mtd: rawnand: qcom: avoid write to unavailable register Sivaprakash Murugesan
@ 2020-06-12 6:49 ` Sivaprakash Murugesan
2020-06-12 7:23 ` Miquel Raynal
1 sibling, 1 reply; 5+ messages in thread
From: Sivaprakash Murugesan @ 2020-06-12 6:49 UTC (permalink / raw)
To: miquel.raynal, richard, vigneshr, peter.ujfalusi, sivaprak,
boris.brezillon, architt, linux-mtd, linux-kernel
BAM is DMA controller on QCOM ipq platforms, BAM mode on NAND driver
is set by writing BAM_MODE_EN bit on NAND_CTRL register.
NAND_CTRL is an operational register and in BAM mode operational
registers are read only.
So, before writing into NAND_CTRL register check if BAM mode is already
enabled by bootloader, and set BAM mode only if it is not set already.
Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
---
[V3]
* Changed commit message to give a small info about BAM
drivers/mtd/nand/raw/qcom_nandc.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
index e0c55bb..4827edd 100644
--- a/drivers/mtd/nand/raw/qcom_nandc.c
+++ b/drivers/mtd/nand/raw/qcom_nandc.c
@@ -2784,7 +2784,14 @@ static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
/* enable ADM or BAM DMA */
if (nandc->props->is_bam) {
nand_ctrl = nandc_read(nandc, NAND_CTRL);
- nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN);
+ /* NAND_CTRL is an operational registers, and CPU
+ * access to operational registers are read only
+ * in BAM mode. So update the NAND_CTRL register
+ * only if it is not in BAM mode. In most cases BAM
+ * mode will be enabled in bootloader
+ */
+ if (!(nand_ctrl | BAM_MODE_EN))
+ nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN);
} else {
nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
}
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH V3 1/2] mtd: rawnand: qcom: avoid write to unavailable register
2020-06-12 6:49 ` [PATCH V3 1/2] mtd: rawnand: qcom: avoid write to unavailable register Sivaprakash Murugesan
@ 2020-06-12 7:16 ` Miquel Raynal
0 siblings, 0 replies; 5+ messages in thread
From: Miquel Raynal @ 2020-06-12 7:16 UTC (permalink / raw)
To: Sivaprakash Murugesan
Cc: richard, vigneshr, peter.ujfalusi, boris.brezillon, architt,
linux-mtd, linux-kernel, stable
Hi Sivaprakash,
Sivaprakash Murugesan <sivaprak@codeaurora.org> wrote on Fri, 12 Jun
2020 12:19:48 +0530:
> SFLASHC_BURST_CFG is only available on older ipq nand platforms, this
> register has been removed when the NAND controller is moved as part of qpic
> controller.
>
> avoid register writes to this register on devices which are based on qpic
Avoid writing this register on ...
> NAND controllers.
>
> Fixes: a0637834 (mtd: nand: qcom: support for IPQ4019 QPIC NANDcontroller)
> Fixes: dce84760 (mtd: nand: qcom: Support for IPQ8074 QPIC NAND controller)
I don't think having two Fixes tag is allowed. Take the older one
instead.
> Cc: stable@vger.kernel.org
> Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
> ---
> [V3]
> * Addressed Miquel comments, added flag based on nand controller hw
> to avoid the register writes to specific ipq platforms
> drivers/mtd/nand/raw/qcom_nandc.c | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
> index f1daf33..e0c55bb 100644
> --- a/drivers/mtd/nand/raw/qcom_nandc.c
> +++ b/drivers/mtd/nand/raw/qcom_nandc.c
> @@ -459,11 +459,13 @@ struct qcom_nand_host {
> * among different NAND controllers.
> * @ecc_modes - ecc mode for NAND
> * @is_bam - whether NAND controller is using BAM
> + * @is_qpic - whether NAND CTRL is part of qpic IP
> * @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset
> */
> struct qcom_nandc_props {
> u32 ecc_modes;
> bool is_bam;
> + bool is_qpic;
> u32 dev_cmd_reg_start;
> };
>
> @@ -2774,7 +2776,8 @@ static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
> u32 nand_ctrl;
>
> /* kill onenand */
> - nandc_write(nandc, SFLASHC_BURST_CFG, 0);
> + if (!nandc->props->is_qpic)
> + nandc_write(nandc, SFLASHC_BURST_CFG, 0);
> nandc_write(nandc, dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD),
> NAND_DEV_CMD_VLD_VAL);
>
> @@ -3029,18 +3032,21 @@ static int qcom_nandc_remove(struct platform_device *pdev)
> static const struct qcom_nandc_props ipq806x_nandc_props = {
> .ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
> .is_bam = false,
> + .is_qpic = false,
This line is unneeded.
> .dev_cmd_reg_start = 0x0,
> };
>
> static const struct qcom_nandc_props ipq4019_nandc_props = {
> .ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
> .is_bam = true,
> + .is_qpic = true,
> .dev_cmd_reg_start = 0x0,
> };
>
> static const struct qcom_nandc_props ipq8074_nandc_props = {
> .ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
> .is_bam = true,
> + .is_qpic = true,
> .dev_cmd_reg_start = 0x7000,
> };
>
Much better patch IMHO, just a few nits and we'll be good.
Thanks,
Miquèl
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH V3 2/2] mtd: rawnand: qcom: set BAM mode only if not set already
2020-06-12 6:49 ` [PATCH V3 2/2] mtd: rawnand: qcom: set BAM mode only if not set already Sivaprakash Murugesan
@ 2020-06-12 7:23 ` Miquel Raynal
0 siblings, 0 replies; 5+ messages in thread
From: Miquel Raynal @ 2020-06-12 7:23 UTC (permalink / raw)
To: Sivaprakash Murugesan
Cc: richard, vigneshr, peter.ujfalusi, boris.brezillon, architt,
linux-mtd, linux-kernel
Hi Sivaprakash,
Sivaprakash Murugesan <sivaprak@codeaurora.org> wrote on Fri, 12 Jun
2020 12:19:49 +0530:
> BAM is DMA controller on QCOM ipq platforms, BAM mode on NAND driver
> is set by writing BAM_MODE_EN bit on NAND_CTRL register.
>
> NAND_CTRL is an operational register and in BAM mode operational
> registers are read only.
>
> So, before writing into NAND_CTRL register check if BAM mode is already
So, before enabling BAM mode by writing the NAND_CTRL register, check
if BAM mode was already enabled by the bootloader.
> enabled by bootloader, and set BAM mode only if it is not set already.
>
> Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
> ---
> [V3]
> * Changed commit message to give a small info about BAM
> drivers/mtd/nand/raw/qcom_nandc.c | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
> index e0c55bb..4827edd 100644
> --- a/drivers/mtd/nand/raw/qcom_nandc.c
> +++ b/drivers/mtd/nand/raw/qcom_nandc.c
> @@ -2784,7 +2784,14 @@ static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
> /* enable ADM or BAM DMA */
> if (nandc->props->is_bam) {
> nand_ctrl = nandc_read(nandc, NAND_CTRL);
> - nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN);
> + /* NAND_CTRL is an operational registers, and CPU
> + * access to operational registers are read only
> + * in BAM mode. So update the NAND_CTRL register
> + * only if it is not in BAM mode. In most cases BAM
BAM mode already (Bootloaders
might have already entered
this mode).
> + * mode will be enabled in bootloader
> + */
> + if (!(nand_ctrl | BAM_MODE_EN))
> + nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN);
> } else {
> nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
> }
Thanks,
Miquèl
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-06-12 7:23 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-06-12 6:49 [PATCH V3 0/2] Fix issues related to register access in IPQ NAND Sivaprakash Murugesan
2020-06-12 6:49 ` [PATCH V3 1/2] mtd: rawnand: qcom: avoid write to unavailable register Sivaprakash Murugesan
2020-06-12 7:16 ` Miquel Raynal
2020-06-12 6:49 ` [PATCH V3 2/2] mtd: rawnand: qcom: set BAM mode only if not set already Sivaprakash Murugesan
2020-06-12 7:23 ` Miquel Raynal
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).