From: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
To: broonie@kernel.org, kdasu.kdev@gmail.com
Cc: linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org,
Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
Subject: [PATCH 1/5] spi: bcm-qspi: Add support for setting BSPI clock
Date: Mon, 15 Jun 2020 16:05:53 +1200 [thread overview]
Message-ID: <20200615040557.2011-2-mark.tomlinson@alliedtelesis.co.nz> (raw)
In-Reply-To: <20200615040557.2011-1-mark.tomlinson@alliedtelesis.co.nz>
On iProc devices (unlike previous BCM SoCs) the clock rate of the SPI
can be set. This patch adds the appropriate code for setting that.
Reviewed-by: Callum Sinclair <callum.sinclair@alliedtelesis.co.nz>
Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
---
drivers/spi/spi-bcm-qspi.c | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/drivers/spi/spi-bcm-qspi.c b/drivers/spi/spi-bcm-qspi.c
index 681d09085175..8fc5b9b3757b 100644
--- a/drivers/spi/spi-bcm-qspi.c
+++ b/drivers/spi/spi-bcm-qspi.c
@@ -117,6 +117,13 @@
#define MSPI_MSPI_STATUS_SPIF BIT(0)
+#define CRU_CTRL_REG 0x0
+#define QSPI_CLK_SEL_25M 0x00
+#define QSPI_CLK_SEL_50M 0x02
+#define QSPI_CLK_SEL_31M25 0x04
+#define QSPI_CLK_SEL_62M5 0x06
+#define QSPI_CLK_SEL_MASK 0x06
+
#define INTR_BASE_BIT_SHIFT 0x02
#define INTR_COUNT 0x07
@@ -170,6 +177,7 @@ enum base_type {
MSPI,
BSPI,
CHIP_SELECT,
+ CRU_CTRL,
BASEMAX,
};
@@ -625,6 +633,7 @@ static void bcm_qspi_update_parms(struct bcm_qspi *qspi,
static int bcm_qspi_setup(struct spi_device *spi)
{
struct bcm_qspi_parms *xp;
+ struct bcm_qspi *qspi = spi_master_get_devdata(spi->master);
if (spi->bits_per_word > 16)
return -EINVAL;
@@ -639,6 +648,21 @@ static int bcm_qspi_setup(struct spi_device *spi)
xp->speed_hz = spi->max_speed_hz;
xp->mode = spi->mode;
+ if (qspi->base[CRU_CTRL]) {
+ u32 tmp = bcm_qspi_read(qspi, CRU_CTRL, CRU_CTRL_REG);
+
+ /* Set BSPI clock rate */
+ tmp &= ~QSPI_CLK_SEL_MASK;
+ if (spi->max_speed_hz >= 62500000)
+ tmp |= QSPI_CLK_SEL_62M5;
+ else if (spi->max_speed_hz >= 50000000)
+ tmp |= QSPI_CLK_SEL_50M;
+ else if (spi->max_speed_hz >= 31250000)
+ tmp |= QSPI_CLK_SEL_31M25;
+ /* default is 25MHz */
+ bcm_qspi_write(qspi, CRU_CTRL, CRU_CTRL_REG, tmp);
+ }
+
if (spi->bits_per_word)
xp->bits_per_word = spi->bits_per_word;
else
@@ -1459,6 +1483,16 @@ int bcm_qspi_probe(struct platform_device *pdev,
qspi->soc_intc = NULL;
}
+ /* iProc BSPI clock is set through CRU control */
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cru_ctrl");
+ if (res) {
+ qspi->base[CRU_CTRL] = devm_ioremap_resource(dev, res);
+ if (IS_ERR(qspi->base[CRU_CTRL])) {
+ ret = PTR_ERR(qspi->base[CRU_CTRL]);
+ goto qspi_probe_err;
+ }
+ }
+
ret = clk_prepare_enable(qspi->clk);
if (ret) {
dev_err(dev, "failed to prepare clock\n");
--
2.27.0
next prev parent reply other threads:[~2020-06-15 4:06 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-15 4:05 [PATCH 0/5] Improvements to spi-bcm-qspi Mark Tomlinson
2020-06-15 4:05 ` Mark Tomlinson [this message]
2020-06-15 4:05 ` [PATCH 2/5] spi: bcm-qspi: Improve debug reading SPI data Mark Tomlinson
2020-06-15 4:05 ` [PATCH 3/5] spi: bcm-qspi: Do not split transfers into small chunks Mark Tomlinson
2020-06-15 13:31 ` Mark Brown
2020-06-15 4:05 ` [PATCH 4/5] spi: bcm-qspi: Make multiple data blocks interrupt-driven Mark Tomlinson
2020-06-15 14:32 ` Mark Brown
2020-06-16 3:07 ` Mark Tomlinson
2020-06-16 8:26 ` Mark Brown
2020-06-15 4:05 ` [PATCH 5/5] spi: bcm-qspi: Improve interrupt handling Mark Tomlinson
2020-06-15 19:05 ` [PATCH 0/5] Improvements to spi-bcm-qspi Kamal Dasu
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