From: Bjorn Helgaas <helgaas@kernel.org>
To: Jim Quinlan <james.quinlan@broadcom.com>
Cc: linux-pci@vger.kernel.org, Christoph Hellwig <hch@lst.de>,
Nicolas Saenz Julienne <nsaenzjulienne@suse.de>,
bcm-kernel-feedback-list@broadcom.com,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Rob Herring <robh@kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>,
Florian Fainelli <f.fainelli@gmail.com>,
"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE"
<linux-rpi-kernel@lists.infradead.org>,
"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE"
<linux-arm-kernel@lists.infradead.org>,
open list <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v5 06/12] PCI: brcmstb: Add bcm7278 PERST support
Date: Tue, 16 Jun 2020 17:05:11 -0500 [thread overview]
Message-ID: <20200616220511.GA1984089@bjorn-Precision-5520> (raw)
In-Reply-To: <20200616205533.3513-7-james.quinlan@broadcom.com>
On Tue, Jun 16, 2020 at 04:55:13PM -0400, Jim Quinlan wrote:
> From: Jim Quinlan <jquinlan@broadcom.com>
>
> The PERST bit was moved to a different register in 7278-type STB chips. In
> addition, the polarity of the bit was also changed; for other chips writing
> a 1 specified assert; for 7278-type chips, writing a 0 specifies assert.
>
> Signal-wise, PERST is an asserted-low signal.
s/PERST/PERST#/ to match usage of the signal name in spec.
The PERST bit above is the name of a register bit, so use whatever
matches the STB spec.
> Signed-off-by: Jim Quinlan <jquinlan@broadcom.com>
> Acked-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
> drivers/pci/controller/pcie-brcmstb.c | 14 +++++++++++---
> 1 file changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
> index 7c148eb65170..d0e256d8578a 100644
> --- a/drivers/pci/controller/pcie-brcmstb.c
> +++ b/drivers/pci/controller/pcie-brcmstb.c
> @@ -83,6 +83,7 @@
>
> #define PCIE_MISC_PCIE_CTRL 0x4064
> #define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK 0x1
> +#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK 0x4
>
> #define PCIE_MISC_PCIE_STATUS 0x4068
> #define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x80
> @@ -685,9 +686,16 @@ static inline void brcm_pcie_perst_set(struct brcm_pcie *pcie, u32 val)
> {
> u32 tmp;
>
> - tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
> - u32p_replace_bits(&tmp, val, PCIE_RGR1_SW_INIT_1_PERST_MASK);
> - writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
> + if (pcie->type == BCM7278) {
> + /* Perst bit has moved and assert value is 0 */
s/Perst/PERST/ or PERST# so it doesn't look like an English word and
to match the STB spec.
> + tmp = readl(pcie->base + PCIE_MISC_PCIE_CTRL);
> + u32p_replace_bits(&tmp, !val, PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK);
> + writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL);
> + } else {
> + tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
> + u32p_replace_bits(&tmp, val, PCIE_RGR1_SW_INIT_1_PERST_MASK);
> + writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
> + }
> }
>
> static inline int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie,
> --
> 2.17.1
>
next prev parent reply other threads:[~2020-06-16 22:05 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-16 20:55 [PATCH v5 00/12] PCI: brcmstb: enable PCIe for STB chips Jim Quinlan
2020-06-16 20:55 ` [PATCH v5 01/12] PCI: brcmstb: PCIE_BRCMSTB depends on ARCH_BRCMSTB Jim Quinlan
2020-06-16 20:55 ` [PATCH v5 02/12] ata: ahci_brcm: Fix use of BCM7216 reset controller Jim Quinlan
2020-06-16 22:04 ` Bjorn Helgaas
2020-06-16 20:55 ` [PATCH v5 03/12] dt-bindings: PCI: Add bindings for more Brcmstb chips Jim Quinlan
2020-06-16 22:05 ` Bjorn Helgaas
2020-06-16 20:55 ` [PATCH v5 04/12] PCI: brcmstb: Add bcm7278 register info Jim Quinlan
2020-06-16 20:55 ` [PATCH v5 05/12] PCI: brcmstb: Add suspend and resume pm_ops Jim Quinlan
2020-06-16 20:55 ` [PATCH v5 06/12] PCI: brcmstb: Add bcm7278 PERST support Jim Quinlan
2020-06-16 22:05 ` Bjorn Helgaas [this message]
2020-06-16 20:55 ` [PATCH v5 07/12] PCI: brcmstb: Add control of rescal reset Jim Quinlan
2020-06-16 22:05 ` Bjorn Helgaas
2020-06-17 17:32 ` Jim Quinlan
2020-06-16 20:55 ` [PATCH v5 09/12] PCI: brcmstb: Set internal memory viewport sizes Jim Quinlan
2020-06-16 22:05 ` Bjorn Helgaas
2020-06-17 17:28 ` Jim Quinlan
2020-06-18 3:01 ` Bjorn Helgaas
2020-06-18 14:56 ` Jim Quinlan
2020-06-16 20:55 ` [PATCH v5 10/12] PCI: brcmstb: Accommodate MSI for older chips Jim Quinlan
2020-06-16 20:55 ` [PATCH v5 11/12] PCI: brcmstb: Set bus max burst size by chip type Jim Quinlan
2020-06-16 20:55 ` [PATCH v5 12/12] PCI: brcmstb: Add bcm7211, bcm7216, bcm7445, bcm7278 to match list Jim Quinlan
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200616220511.GA1984089@bjorn-Precision-5520 \
--to=helgaas@kernel.org \
--cc=bcm-kernel-feedback-list@broadcom.com \
--cc=bhelgaas@google.com \
--cc=f.fainelli@gmail.com \
--cc=hch@lst.de \
--cc=james.quinlan@broadcom.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linux-rpi-kernel@lists.infradead.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=nsaenzjulienne@suse.de \
--cc=robh@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).