From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00234C433E1 for ; Wed, 17 Jun 2020 21:15:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C867521841 for ; Wed, 17 Jun 2020 21:15:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1592428545; bh=v7QKeSKgeC6EKbmPqKylS8p9g9Wks7kPioikxtWP80U=; h=Date:From:To:Cc:Subject:References:In-Reply-To:List-ID:From; b=qA5Jo/QgittxYwGEHZWx1zypzOGK57oQYIWBoll7/IUDx8QDkXsebBGCXar8W2AFe 1EQ7AzgyMRs5G4htfNmkRZaEwF7ruJnpd0PJoaBF8GS9CAvxerjsqPpI6S0GcVOmhH iBK/gXUWbPe2+5rmvR8hklfMkO2p3AwbvDN4eB78= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727011AbgFQVPo (ORCPT ); Wed, 17 Jun 2020 17:15:44 -0400 Received: from mail-io1-f68.google.com ([209.85.166.68]:45541 "EHLO mail-io1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726955AbgFQVPn (ORCPT ); Wed, 17 Jun 2020 17:15:43 -0400 Received: by mail-io1-f68.google.com with SMTP id y5so4577386iob.12; Wed, 17 Jun 2020 14:15:42 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=xI0mlKe2wRYjHDHCCF+79f1gMeJVs47ukTuRHuYoNXw=; b=eo9VmYwsuC/jJIbUh3/iypCmjz09CdD/TssIKYreJkXx3FFH2JN8qgAxkNyL2SW9/c 64I7j6xLyiIrmrCB6y65OyIJ/wlW2KgOaXQ2K+simOndCkm4BTUGomG3Goy7iInROW+d MYCv6fmT4zO65i6ru7kHUna1DQAG2ikB3MQ/zDyxCF6/Dkn6zhdqQwz1w+p9UDVVbzzZ Rb9V9T81sNHBBUaULISQCZ437YbYx9Bh3Ib/vNrUcUxGZT2TtO46hwXSGCxHciBAfDLz TjZvnS3sA5SCbJogmGib/KAEzagvk4BeRpljzRoWhhFZEZrp7wQHiiO91Yzea2JpOKYG bn3w== X-Gm-Message-State: AOAM5315/9WkYjx5SdlIlIE1+8Yx/JO5Vl/2SNQnY1u6MRkaeD0FFXpj 5eO5Fu0ES2cGUpBYMhFFkg== X-Google-Smtp-Source: ABdhPJy9jNQ2ywvtsoluzmREgiIioIKxsPjeXA+erf0DpK8C5v435zxINloN/zcGsS3rvsY1j6EOLA== X-Received: by 2002:a05:6602:1204:: with SMTP id y4mr1523265iot.44.1592428542398; Wed, 17 Jun 2020 14:15:42 -0700 (PDT) Received: from xps15 ([64.188.179.253]) by smtp.gmail.com with ESMTPSA id l16sm398139ilm.58.2020.06.17.14.15.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Jun 2020 14:15:42 -0700 (PDT) Received: (nullmailer pid 2835354 invoked by uid 1000); Wed, 17 Jun 2020 21:15:41 -0000 Date: Wed, 17 Jun 2020 15:15:41 -0600 From: Rob Herring To: Yifeng Zhao Cc: miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, devicetree@vger.kernel.org, linux-mtd@lists.infradead.org, heiko@sntech.de, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v6 1/8] dt-bindings: mtd: Describe Rockchip RK3xxx NAND flash controller Message-ID: <20200617211541.GB2811091@bogus> References: <20200609074020.23860-1-yifeng.zhao@rock-chips.com> <20200609074020.23860-2-yifeng.zhao@rock-chips.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200609074020.23860-2-yifeng.zhao@rock-chips.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Jun 09, 2020 at 03:40:18PM +0800, Yifeng Zhao wrote: > Documentation support for Rockchip RK3xxx NAND flash controllers > > Signed-off-by: Yifeng Zhao > --- > > Changes in v6: > - Fix some wrong define > - Modified the definition of compatible > > Changes in v5: > - Fix some wrong define > - Add boot-medium define > - Remove some compatible define > > Changes in v4: > - The compatible define with rkxx_nfc > - Add assigned-clocks > - Fix some wrong define > > Changes in v3: > - Change the title for the dt-bindings > > Changes in v2: None > > .../mtd/rockchip,nand-controller.yaml | 154 ++++++++++++++++++ > 1 file changed, 154 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mtd/rockchip,nand-controller.yaml > > diff --git a/Documentation/devicetree/bindings/mtd/rockchip,nand-controller.yaml b/Documentation/devicetree/bindings/mtd/rockchip,nand-controller.yaml > new file mode 100644 > index 000000000000..f753fe8248aa > --- /dev/null > +++ b/Documentation/devicetree/bindings/mtd/rockchip,nand-controller.yaml > @@ -0,0 +1,154 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/mtd/rockchip,nand-controller.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Rockchip SoCs NAND FLASH Controller (NFC) > + > +allOf: > + - $ref: "nand-controller.yaml#" > + > +maintainers: > + - Heiko Stuebner > + > +properties: > + compatible: > + oneOf: > + - const: rockchip,px30-nfc > + - const: rockchip,rk2928-nfc > + - const: rockchip,rv1108-nfc > + - items: > + - const: rockchip,rk3326-nfc > + - const: rockchip,px30-nfc > + - items: > + - const: rockchip,rk3036-nfc > + - const: rockchip,rk2928-nfc > + - items: > + - const: rockchip,rk3308-nfc > + - const: rockchip,rv1108-nfc > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + minItems: 1 > + items: > + - description: Bus Clock > + - description: Module Clock > + > + clock-names: > + minItems: 1 > + items: > + - const: ahb > + - const: nfc > + > + assigned-clocks: > + maxItems: 1 > + > + assigned-clock-rates: > + maxItems: 1 > + > + pinctrl-0: > + maxItems: 1 > + > + pinctrl-names: > + const: default > + > + power-domains: > + maxItems: 1 > + > +patternProperties: > + "^nand@[a-f0-9]$": > + type: object > + properties: > + reg: > + minimum: 0 > + maximum: 7 > + > + nand-ecc-mode: > + const: hw > + > + nand-ecc-step-size: > + const: 1024 > + > + nand-ecc-strength: > + enum: [16, 24, 40, 60, 70] > + description: This needs a '|' at the end if you want the below line breaks preserved. > + The ECC configurations that can be supported are as follows. > + - NFCv900(PX30 and RK3326) support ecc strength 16, 40, 60 and 70. > + - NFCv600(RK3066 and RK2928) support ecc strength 16, 24, 40 and 60. > + - NFCv622(RK3036 and RK3128) support ecc strength 16, 24, 40 and 60. > + - NFCv800(RK3308 and RV1108) support ecc strength 16. > + > + nand-bus-width: > + const: 8 > + > + rockchip,boot-blks: > + minimum: 2 > + default: 16 > + allOf: > + - $ref: /schemas/types.yaml#/definitions/uint32 > + description: > + The NFC driver need this information to select ECC > + algorithms supported by the BOOTROM. > + Only used in combination with 'nand-is-boot-medium'. > + > + rockchip,boot-ecc-strength: > + enum: [16, 24, 40, 60, 70] > + allOf: > + - $ref: /schemas/types.yaml#/definitions/uint32 > + description: > + If specified it indicates that a different BCH/ECC setting is > + supported by the BOOTROM. > + - NFCv900(PX30 and RK3326) support ecc strength 16 and 70. > + - NFCv600(RK3066 and RK2928) support ecc strength 16, 24, 40 and 60. > + - NFCv622(RK3036 and RK3128) support ecc strength 16, 24, 40 and 60. > + - NFCv800(RK3308 and RV1108) support ecc strength 16. > + Only used in combination with 'nand-is-boot-medium'. > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + - clock-names > + > +examples: > + - | > + #include > + #include > + nfc: nand-controller@ff4b0000 { > + compatible = "rockchip,rk3308-nfc", > + "rockchip,rv1108-nfc"; > + reg = <0x0 0xff4b0000 0x0 0x4000>; > + interrupts = ; > + clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; > + clock-names = "ahb", "nfc"; > + assigned-clocks = <&clks SCLK_NANDC>; > + assigned-clock-rates = <150000000>; > + > + pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0 > + &flash_rdn &flash_rdy &flash_wrn>; > + pinctrl-names = "default"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + nand@0 { > + reg = <0>; > + label = "rk-nand"; > + nand-bus-width = <8>; > + nand-ecc-mode = "hw"; > + nand-ecc-step-size = <1024>; > + nand-ecc-strength = <16>; > + nand-is-boot-medium; > + rockchip,boot-blks = <8>; > + rockchip,boot-ecc-strength = <16>; > + }; > + }; > + > +... > -- > 2.17.1 > > >