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From: Vishal Sagar <vishal.sagar@xilinx.com>
To: hyunk@xilinx.com, laurent.pinchart@ideasonboard.com,
	hverkuil@xs4all.nl, mchehab@kernel.org, robh+dt@kernel.org,
	mark.rutland@arm.com, michals@xilinx.com,
	linux-media@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, joe@perches.com
Cc: sandipk@xilinx.com, dineshk@xilinx.com,
	Vishal Sagar <vishal.sagar@xilinx.com>
Subject: [PATCH v3 1/3] v4l2-dv-timings: Add timings for 1920x1080P48 and 4KP48
Date: Thu, 18 Jun 2020 11:03:02 +0530	[thread overview]
Message-ID: <20200618053304.14551-2-vishal.sagar@xilinx.com> (raw)
In-Reply-To: <20200618053304.14551-1-vishal.sagar@xilinx.com>

Add the timing entry for 1920x1080p48, 3840x2160p48 and 4096x2160p48
from CTA-861-G.
1920x1080p48 is VIC 111.
3840x2160P48 is VIC 114.
4096x2160P48 is VIC 115.

Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
---
v3
- Added for first time

 include/uapi/linux/v4l2-dv-timings.h | 31 +++++++++++++++++++++++++++-
 1 file changed, 30 insertions(+), 1 deletion(-)

diff --git a/include/uapi/linux/v4l2-dv-timings.h b/include/uapi/linux/v4l2-dv-timings.h
index b52b67c62562..6ceaa7841923 100644
--- a/include/uapi/linux/v4l2-dv-timings.h
+++ b/include/uapi/linux/v4l2-dv-timings.h
@@ -167,6 +167,16 @@
 		V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 20) \
 }
 
+#define V4L2_DV_BT_CEA_1920X1080P48 { \
+	.type = V4L2_DV_BT_656_1120, \
+	V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
+		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+		148500000, 638, 44, 148, 4, 5, 36, 0, 0, 0, \
+		V4L2_DV_BT_STD_CEA861, \
+		V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+		V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 111) \
+}
+
 #define V4L2_DV_BT_CEA_1920X1080P50 { \
 	.type = V4L2_DV_BT_656_1120, \
 	V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
@@ -229,6 +239,16 @@
 		{ 0, 0 }, 95, 1) \
 }
 
+#define V4L2_DV_BT_CEA_3840X2160P48 { \
+	.type = V4L2_DV_BT_656_1120, \
+	V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
+		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+		594000000, 1276, 88, 296, 8, 10, 72, 0, 0, 0, \
+		V4L2_DV_BT_STD_CEA861, \
+		V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+		V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 114) \
+}
+
 #define V4L2_DV_BT_CEA_3840X2160P50 { \
 	.type = V4L2_DV_BT_656_1120, \
 	V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
@@ -278,6 +298,16 @@
 		V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 100) \
 }
 
+#define V4L2_DV_BT_CEA_4096X2160P48 { \
+	.type = V4L2_DV_BT_656_1120, \
+	V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
+		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+		594000000, 1020, 88, 296, 8, 10, 72, 0, 0, 0, \
+		V4L2_DV_BT_STD_CEA861, \
+		V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+		V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 115) \
+}
+
 #define V4L2_DV_BT_CEA_4096X2160P50 { \
 	.type = V4L2_DV_BT_656_1120, \
 	V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
@@ -297,7 +327,6 @@
 		V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 102) \
 }
 
-
 /* VESA Discrete Monitor Timings as per version 1.0, revision 12 */
 
 #define V4L2_DV_BT_DMT_640X350P85 { \
-- 
2.21.0


  reply	other threads:[~2020-06-18  5:33 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-18  5:33 [PATCH v3 0/3] Add support for Xilinx UHD-SDI Receiver subsystem Vishal Sagar
2020-06-18  5:33 ` Vishal Sagar [this message]
2020-07-15 16:16   ` [PATCH v3 1/3] v4l2-dv-timings: Add timings for 1920x1080P48 and 4KP48 Laurent Pinchart
2020-06-18  5:33 ` [PATCH v3 2/3] media: dt-bindings: media: xilinx: Add Xilinx UHD-SDI Receiver Subsystem Vishal Sagar
2020-07-13 18:54   ` Rob Herring
2020-07-15 16:29     ` Laurent Pinchart
2020-08-19 13:45       ` Vishal Sagar
2020-08-19 16:40         ` Laurent Pinchart
2020-08-24  1:00           ` Laurent Pinchart
2020-06-18  5:33 ` [PATCH v3 3/3] media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem driver Vishal Sagar
2020-06-25  9:43   ` Hans Verkuil
2020-07-15 21:33     ` Laurent Pinchart
2020-08-19 13:47       ` Vishal Sagar
2020-08-19 16:56         ` Laurent Pinchart
2020-08-26 14:10           ` Nicolas Dufresne
2020-08-26 14:50             ` Vishal Sagar
2020-09-10 10:22             ` Hans Verkuil
2020-09-15  2:38               ` Laurent Pinchart
2020-09-15  8:31                 ` Hans Verkuil
2020-08-19 13:47     ` Vishal Sagar
2020-07-15 22:42   ` Hyun Kwon
2020-08-19 13:48     ` Vishal Sagar

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