From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 264B1C433DF for ; Mon, 22 Jun 2020 08:17:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EF5472068F for ; Mon, 22 Jun 2020 08:17:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="f5fFAa+G" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726778AbgFVIRu (ORCPT ); Mon, 22 Jun 2020 04:17:50 -0400 Received: from mail29.static.mailgun.info ([104.130.122.29]:18511 "EHLO mail29.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726695AbgFVIRu (ORCPT ); Mon, 22 Jun 2020 04:17:50 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1592813869; h=Content-Transfer-Encoding: MIME-Version: References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=glcto0l0iQlHpS80rrXSQWxQLrQAV2ARSJlihUlAAiA=; b=f5fFAa+GLIPvJXZ0d2BlqKWdBkYj4MpHU06AcYn64iUTyMFSOqEyGk6kSwDmpsJbT9Ln4TVE YI7FkygCfJxg89/Y6WqYYNgAnnnpbpfoDiDkkHcvHwoJxa89f+mg/AVoNSy04QfEP5vgJ6JG 42OBE1mCvmWAfsGadY00BLSxmtQ= X-Mailgun-Sending-Ip: 104.130.122.29 X-Mailgun-Sid: WyI0MWYwYSIsICJsaW51eC1rZXJuZWxAdmdlci5rZXJuZWwub3JnIiwgImJlOWU0YSJd Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n10.prod.us-east-1.postgun.com with SMTP id 5ef069200206ad41d1a25260 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Mon, 22 Jun 2020 08:17:36 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 28E2DC4344A; Mon, 22 Jun 2020 08:17:36 +0000 (UTC) Received: from blr-ubuntu-253.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: sibis) by smtp.codeaurora.org (Postfix) with ESMTPSA id BB9F8C4339C; Mon, 22 Jun 2020 08:17:29 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org BB9F8C4339C Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=sibis@codeaurora.org From: Sibi Sankar To: viresh.kumar@linaro.org, sboyd@kernel.org, georgi.djakov@linaro.org, saravanak@google.com, mka@chromium.org Cc: nm@ti.com, bjorn.andersson@linaro.org, agross@kernel.org, rjw@rjwysocki.net, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dianders@chromium.org, vincent.guittot@linaro.org, amit.kucheria@linaro.org, lukasz.luba@arm.com, sudeep.holla@arm.com, smasetty@codeaurora.org, Sibi Sankar Subject: [PATCH v6 5/5] cpufreq: qcom: Disable fast switch when scaling DDR/L3 Date: Mon, 22 Jun 2020 13:46:49 +0530 Message-Id: <20200622081649.27280-6-sibis@codeaurora.org> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20200622081649.27280-1-sibis@codeaurora.org> References: <20200622081649.27280-1-sibis@codeaurora.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Disable fast switch when the opp-tables required for scaling DDR/L3 are populated. Reviewed-by: Matthias Kaehlcke Signed-off-by: Sibi Sankar --- v7: * Picked up R-b from Matthias v6: * No change v5: * Drop dev_pm_opp_get_path_count [Saravana] drivers/cpufreq/qcom-cpufreq-hw.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c index aaf98333d37da..fa68fa8ebd95e 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -159,6 +159,7 @@ static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev, dev_err(cpu_dev, "Invalid opp table in device tree\n"); return ret; } else { + policy->fast_switch_possible = true; icc_scaling_enabled = false; } @@ -308,8 +309,6 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) dev_pm_opp_of_register_em(policy->cpus); - policy->fast_switch_possible = true; - return 0; error: devm_iounmap(dev, base); -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project