From: Matthias Kaehlcke <mka@chromium.org>
To: Rajendra Nayak <rnayak@codeaurora.org>
Cc: viresh.kumar@linaro.org, sboyd@kernel.org,
bjorn.andersson@linaro.org, agross@kernel.org,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 04/17] arm64: dts: sc7180: Add OPP table for all qup devices
Date: Thu, 25 Jun 2020 08:17:13 -0700 [thread overview]
Message-ID: <20200625151713.GF39073@google.com> (raw)
In-Reply-To: <1588080785-6812-5-git-send-email-rnayak@codeaurora.org>
Hi Rajendra,
On Tue, Apr 28, 2020 at 07:02:52PM +0530, Rajendra Nayak wrote:
> qup has a requirement to vote on the performance state of the CX domain
> in sc7180 devices. Add OPP tables for these and also add power-domains
> property for all qup instances.
>
> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
> ---
> arch/arm64/boot/dts/qcom/sc7180.dtsi | 79 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 79 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> index 998f101..efba600 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -417,6 +417,25 @@
> status = "disabled";
> };
>
> + qup_opp_table: qup-opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-75000000 {
> + opp-hz = /bits/ 64 <75000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-100000000 {
> + opp-hz = /bits/ 64 <100000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + };
> +
> + opp-128000000 {
> + opp-hz = /bits/ 64 <128000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + };
> + };
> +
> qupv3_id_0: geniqup@8c0000 {
> compatible = "qcom,geni-se-qup";
> reg = <0 0x008c0000 0 0x6000>;
no entries for i2c0?
> @@ -452,6 +471,8 @@
> interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> + power-domains = <&rpmhpd SC7180_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> status = "disabled";
> };
>
> @@ -463,6 +484,8 @@
> pinctrl-names = "default";
> pinctrl-0 = <&qup_uart0_default>;
> interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&rpmhpd SC7180_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> status = "disabled";
> };
>
> @@ -476,6 +499,8 @@
> interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> + power-domains = <&rpmhpd SC7180_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> status = "disabled";
> };
>
> @@ -489,6 +514,8 @@
> interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> + power-domains = <&rpmhpd SC7180_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> status = "disabled";
> };
>
> @@ -500,6 +527,8 @@
> pinctrl-names = "default";
> pinctrl-0 = <&qup_uart1_default>;
> interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&rpmhpd SC7180_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> status = "disabled";
> };
>
> @@ -513,6 +542,8 @@
> interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> + power-domains = <&rpmhpd SC7180_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> status = "disabled";
> };
>
> @@ -524,6 +555,8 @@
> pinctrl-names = "default";
> pinctrl-0 = <&qup_uart2_default>;
> interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&rpmhpd SC7180_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> status = "disabled";
> };
>
> @@ -537,6 +570,8 @@
> interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> + power-domains = <&rpmhpd SC7180_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> status = "disabled";
> };
>
> @@ -550,6 +585,8 @@
> interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> + power-domains = <&rpmhpd SC7180_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> status = "disabled";
> };
>
> @@ -561,6 +598,8 @@
> pinctrl-names = "default";
> pinctrl-0 = <&qup_uart3_default>;
> interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&rpmhpd SC7180_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> status = "disabled";
> };
>
> @@ -574,6 +613,8 @@
> interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> + power-domains = <&rpmhpd SC7180_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> status = "disabled";
> };
>
> @@ -585,6 +626,8 @@
> pinctrl-names = "default";
> pinctrl-0 = <&qup_uart4_default>;
> interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&rpmhpd SC7180_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> status = "disabled";
> };
>
> @@ -598,6 +641,8 @@
> interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> + power-domains = <&rpmhpd SC7180_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> status = "disabled";
> };
>
> @@ -611,6 +656,8 @@
> interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> + power-domains = <&rpmhpd SC7180_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> status = "disabled";
> };
>
> @@ -622,6 +669,8 @@
> pinctrl-names = "default";
> pinctrl-0 = <&qup_uart5_default>;
> interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&rpmhpd SC7180_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> status = "disabled";
> };
> };
no entries for i2c6?
> @@ -661,6 +710,8 @@
> interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> + power-domains = <&rpmhpd SC7180_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> status = "disabled";
> };
>
> @@ -672,6 +723,8 @@
> pinctrl-names = "default";
> pinctrl-0 = <&qup_uart6_default>;
> interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&rpmhpd SC7180_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> status = "disabled";
> };
>
> @@ -685,6 +738,8 @@
> interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> + power-domains = <&rpmhpd SC7180_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> status = "disabled";
> };
>
> @@ -696,6 +751,8 @@
> pinctrl-names = "default";
> pinctrl-0 = <&qup_uart7_default>;
> interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&rpmhpd SC7180_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> status = "disabled";
> };
>
> @@ -709,6 +766,8 @@
> interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> + power-domains = <&rpmhpd SC7180_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> status = "disabled";
> };
>
> @@ -722,6 +781,8 @@
> interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> + power-domains = <&rpmhpd SC7180_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> status = "disabled";
> };
>
> @@ -733,6 +794,8 @@
> pinctrl-names = "default";
> pinctrl-0 = <&qup_uart8_default>;
> interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&rpmhpd SC7180_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> status = "disabled";
> };
>
> @@ -746,6 +809,8 @@
> interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> + power-domains = <&rpmhpd SC7180_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> status = "disabled";
> };
>
> @@ -757,6 +822,8 @@
> pinctrl-names = "default";
> pinctrl-0 = <&qup_uart9_default>;
> interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&rpmhpd SC7180_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> status = "disabled";
> };
>
> @@ -770,6 +837,8 @@
> interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> + power-domains = <&rpmhpd SC7180_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> status = "disabled";
> };
>
> @@ -783,6 +852,8 @@
> interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> + power-domains = <&rpmhpd SC7180_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> status = "disabled";
> };
>
> @@ -794,6 +865,8 @@
> pinctrl-names = "default";
> pinctrl-0 = <&qup_uart10_default>;
> interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&rpmhpd SC7180_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> status = "disabled";
> };
>
> @@ -807,6 +880,8 @@
> interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> + power-domains = <&rpmhpd SC7180_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> status = "disabled";
> };
>
> @@ -820,6 +895,8 @@
> interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> + power-domains = <&rpmhpd SC7180_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> status = "disabled";
> };
>
> @@ -831,6 +908,8 @@
> pinctrl-names = "default";
> pinctrl-0 = <&qup_uart11_default>;
> interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&rpmhpd SC7180_CX>;
> + operating-points-v2 = <&qup_opp_table>;
> status = "disabled";
> };
> }
next prev parent reply other threads:[~2020-06-25 15:17 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-28 13:32 [PATCH v3 00/17] DVFS for IO devices on sdm845 and sc7180 Rajendra Nayak
2020-04-28 13:32 ` [PATCH v3 01/17] tty: serial: qcom_geni_serial: Use OPP API to set clk/perf state Rajendra Nayak
2020-04-28 22:49 ` Matthias Kaehlcke
2020-04-28 13:32 ` [PATCH v3 02/17] spi: spi-geni-qcom: " Rajendra Nayak
2020-04-28 23:04 ` Matthias Kaehlcke
2020-04-28 13:32 ` [PATCH v3 03/17] arm64: dts: sdm845: Add OPP table for all qup devices Rajendra Nayak
2020-04-29 0:02 ` Matthias Kaehlcke
2020-04-29 14:15 ` Rajendra Nayak
2020-04-29 14:53 ` Rajendra Nayak
2020-04-29 16:10 ` Matthias Kaehlcke
2020-04-29 16:38 ` Rajendra Nayak
2020-04-30 6:15 ` Viresh Kumar
2020-04-28 13:32 ` [PATCH v3 04/17] arm64: dts: sc7180: " Rajendra Nayak
2020-06-25 15:17 ` Matthias Kaehlcke [this message]
2020-06-29 11:24 ` Rajendra Nayak
2020-04-28 13:32 ` [PATCH v3 05/17] drm/msm/dpu: Use OPP API to set clk/perf state Rajendra Nayak
2020-04-28 16:32 ` Rob Clark
2020-04-29 14:07 ` Rajendra Nayak
2020-04-29 0:14 ` Matthias Kaehlcke
2020-04-29 14:16 ` Rajendra Nayak
2020-04-28 13:32 ` [PATCH v3 06/17] drm/msm: dsi: " Rajendra Nayak
2020-04-28 13:32 ` [PATCH v3 07/17] arm64: dts: sdm845: Add DSI and MDP OPP tables and power-domains Rajendra Nayak
2020-04-29 0:27 ` Matthias Kaehlcke
2020-04-29 14:18 ` Rajendra Nayak
2020-04-28 13:32 ` [PATCH v3 08/17] arm64: dts: sc7180: " Rajendra Nayak
2020-04-28 13:32 ` [PATCH v3 09/17] mmc: sdhci-msm: Fix error handling for dev_pm_opp_of_add_table() Rajendra Nayak
2020-04-28 18:29 ` Ulf Hansson
2020-04-29 14:09 ` Rajendra Nayak
2020-05-05 11:33 ` Ulf Hansson
2020-05-05 13:32 ` Rajendra Nayak
2020-04-28 13:32 ` [PATCH v3 10/17] arm64: dts: sdm845: Add sdhc opps and power-domains Rajendra Nayak
2020-04-28 13:32 ` [PATCH v3 11/17] arm64: dts: sc7180: " Rajendra Nayak
2020-04-28 13:33 ` [PATCH v3 12/17] media: venus: core: Add support for opp tables/perf voting Rajendra Nayak
2020-04-29 0:39 ` Matthias Kaehlcke
2020-04-29 14:19 ` Rajendra Nayak
2020-04-29 14:36 ` Stanimir Varbanov
2020-04-29 15:10 ` Rajendra Nayak
2020-04-28 13:33 ` [PATCH v3 13/17] arm64: dts: sdm845: Add OPP tables and power-domains for venus Rajendra Nayak
2020-04-29 0:42 ` Matthias Kaehlcke
2020-04-28 13:33 ` [PATCH v3 14/17] arm64: dts: sc7180: " Rajendra Nayak
2020-04-28 13:33 ` [PATCH v3 15/17] spi: spi-qcom-qspi: Use OPP API to set clk/perf state Rajendra Nayak
2020-04-29 0:49 ` Matthias Kaehlcke
2020-04-29 14:21 ` Rajendra Nayak
2020-04-28 13:33 ` [PATCH v3 16/17] arm64: dts: sdm845: Add qspi opps and power-domains Rajendra Nayak
2020-04-29 0:52 ` Matthias Kaehlcke
2020-04-28 13:33 ` [PATCH v3 17/17] arm64: dts: sc7180: " Rajendra Nayak
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