* [PATCH v2 0/6] Add RMU and DMAC/GPIO clock support for Actions Semi S500 SoCs
@ 2020-06-24 17:47 Cristian Ciocaltea
2020-06-24 17:47 ` [PATCH v2 1/6] clk: actions: Fix h_clk for Actions S500 SoC Cristian Ciocaltea
` (5 more replies)
0 siblings, 6 replies; 14+ messages in thread
From: Cristian Ciocaltea @ 2020-06-24 17:47 UTC (permalink / raw)
To: Stephen Boyd, Andreas Färber, Manivannan Sadhasivam,
Rob Herring, Michael Turquette, Philipp Zabel
Cc: linux-kernel, linux-clk, linux-arm-kernel, devicetree, linux-actions
This patch series is a stripped-down revision of the initial series
"[PATCH 00/11] Add CMU/RMU/DMA support for Actions Semi S500 SoCs":
https://lore.kernel.org/lkml/cover.1592407030.git.cristian.ciocaltea@gmail.com/
At Stephen's request, I detached all DTS related work to keep the focus
exclusively on the Actions S500 SoC clock driver changes:
- Add support for some missing clocks: APB, DMAC, GPIO
- Add support for Reset Management Unit
The removed patches are subject to resubmission via a separate series:
- arm: dts: owl-s500: Add Clock Management Unit
- arm: dts: owl-s500: Set UART clock refs from CMU
- arm: dts: owl-s500-roseapplepi: Use UART clock from CMU
- arm: dts: owl-s500: Add DMA controller
- arm: dts: owl-s500: Add Reset Controller support
Regards,
Cristi
Changes in v1:
- Incorporate Stephen's review comments
- Remove DTS related patches
- Rebase remaining patches on v5.8-rc2
- Update cover letter, both subject and content, to reflect the new
scope
Cristian Ciocaltea (6):
clk: actions: Fix h_clk for Actions S500 SoC
dt-bindings: clock: Add APB, DMAC, GPIO bindings for Actions S500 SoC
clk: actions: Add APB, DMAC, GPIO clock support for Actions S500 SoC
dt-bindings: reset: Add binding constants for Actions S500 RMU
clk: actions: Add Actions S500 SoC Reset Management Unit support
MAINTAINERS: Add reset binding entry for Actions Semi Owl SoCs
MAINTAINERS | 1 +
drivers/clk/actions/owl-s500.c | 89 ++++++++++++++++++-
include/dt-bindings/clock/actions,s500-cmu.h | 77 ++++++++--------
.../dt-bindings/reset/actions,s500-reset.h | 67 ++++++++++++++
4 files changed, 196 insertions(+), 38 deletions(-)
create mode 100644 include/dt-bindings/reset/actions,s500-reset.h
--
2.27.0
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 1/6] clk: actions: Fix h_clk for Actions S500 SoC
2020-06-24 17:47 [PATCH v2 0/6] Add RMU and DMAC/GPIO clock support for Actions Semi S500 SoCs Cristian Ciocaltea
@ 2020-06-24 17:47 ` Cristian Ciocaltea
2020-06-26 13:45 ` Manivannan Sadhasivam
2020-06-24 17:47 ` [PATCH v2 2/6] dt-bindings: clock: Add APB, DMAC, GPIO bindings " Cristian Ciocaltea
` (4 subsequent siblings)
5 siblings, 1 reply; 14+ messages in thread
From: Cristian Ciocaltea @ 2020-06-24 17:47 UTC (permalink / raw)
To: Stephen Boyd, Andreas Färber, Manivannan Sadhasivam,
Rob Herring, Michael Turquette, Philipp Zabel
Cc: linux-kernel, linux-clk, linux-arm-kernel, devicetree, linux-actions
The h_clk clock in the Actions Semi S500 SoC clock driver has an
invalid parent. Replace with the correct one.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
---
drivers/clk/actions/owl-s500.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c
index e2007ac4d235..0eb83a0b70bc 100644
--- a/drivers/clk/actions/owl-s500.c
+++ b/drivers/clk/actions/owl-s500.c
@@ -183,7 +183,7 @@ static OWL_GATE(timer_clk, "timer_clk", "hosc", CMU_DEVCLKEN1, 27, 0, 0);
static OWL_GATE(hdmi_clk, "hdmi_clk", "hosc", CMU_DEVCLKEN1, 3, 0, 0);
/* divider clocks */
-static OWL_DIVIDER(h_clk, "h_clk", "ahbprevdiv_clk", CMU_BUSCLK1, 12, 2, NULL, 0, 0);
+static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 12, 2, NULL, 0, 0);
static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "ethernet_pll_clk", CMU_ETHERNETPLL, 1, 1, rmii_ref_div_table, 0, 0);
/* factor clocks */
--
2.27.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 2/6] dt-bindings: clock: Add APB, DMAC, GPIO bindings for Actions S500 SoC
2020-06-24 17:47 [PATCH v2 0/6] Add RMU and DMAC/GPIO clock support for Actions Semi S500 SoCs Cristian Ciocaltea
2020-06-24 17:47 ` [PATCH v2 1/6] clk: actions: Fix h_clk for Actions S500 SoC Cristian Ciocaltea
@ 2020-06-24 17:47 ` Cristian Ciocaltea
[not found] ` <159303816030.62212.1603754983340876289@swboyd.mtv.corp.google.com>
2020-06-24 17:47 ` [PATCH v2 3/6] clk: actions: Add APB, DMAC, GPIO clock support " Cristian Ciocaltea
` (3 subsequent siblings)
5 siblings, 1 reply; 14+ messages in thread
From: Cristian Ciocaltea @ 2020-06-24 17:47 UTC (permalink / raw)
To: Stephen Boyd, Andreas Färber, Manivannan Sadhasivam,
Rob Herring, Michael Turquette, Philipp Zabel
Cc: linux-kernel, linux-clk, linux-arm-kernel, devicetree, linux-actions
Add the missing APB, DMAC and GPIO clock bindings constants for
Actions Semi S500 SoC.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
---
include/dt-bindings/clock/actions,s500-cmu.h | 77 ++++++++++----------
1 file changed, 40 insertions(+), 37 deletions(-)
diff --git a/include/dt-bindings/clock/actions,s500-cmu.h b/include/dt-bindings/clock/actions,s500-cmu.h
index 030981cd2d56..a391d1651257 100644
--- a/include/dt-bindings/clock/actions,s500-cmu.h
+++ b/include/dt-bindings/clock/actions,s500-cmu.h
@@ -33,45 +33,48 @@
#define CLK_BISP 15
#define CLK_VCE 16
#define CLK_VDE 17
+#define CLK_APB 18
+#define CLK_DMAC 19
/* peripheral device clock */
-#define CLK_TIMER 18
-#define CLK_I2C0 19
-#define CLK_I2C1 20
-#define CLK_I2C2 21
-#define CLK_I2C3 22
-#define CLK_PWM0 23
-#define CLK_PWM1 24
-#define CLK_PWM2 25
-#define CLK_PWM3 26
-#define CLK_PWM4 27
-#define CLK_PWM5 28
-#define CLK_SD0 29
-#define CLK_SD1 30
-#define CLK_SD2 31
-#define CLK_SENSOR0 32
-#define CLK_SENSOR1 33
-#define CLK_SPI0 34
-#define CLK_SPI1 35
-#define CLK_SPI2 36
-#define CLK_SPI3 37
-#define CLK_UART0 38
-#define CLK_UART1 39
-#define CLK_UART2 40
-#define CLK_UART3 41
-#define CLK_UART4 42
-#define CLK_UART5 43
-#define CLK_UART6 44
-#define CLK_DE1 45
-#define CLK_DE2 46
-#define CLK_I2SRX 47
-#define CLK_I2STX 48
-#define CLK_HDMI_AUDIO 49
-#define CLK_HDMI 50
-#define CLK_SPDIF 51
-#define CLK_NAND 52
-#define CLK_ECC 53
-#define CLK_RMII_REF 54
+#define CLK_GPIO 20
+#define CLK_TIMER 21
+#define CLK_I2C0 22
+#define CLK_I2C1 23
+#define CLK_I2C2 24
+#define CLK_I2C3 25
+#define CLK_PWM0 26
+#define CLK_PWM1 27
+#define CLK_PWM2 28
+#define CLK_PWM3 29
+#define CLK_PWM4 30
+#define CLK_PWM5 31
+#define CLK_SD0 32
+#define CLK_SD1 33
+#define CLK_SD2 34
+#define CLK_SENSOR0 35
+#define CLK_SENSOR1 36
+#define CLK_SPI0 37
+#define CLK_SPI1 38
+#define CLK_SPI2 39
+#define CLK_SPI3 40
+#define CLK_UART0 41
+#define CLK_UART1 42
+#define CLK_UART2 43
+#define CLK_UART3 44
+#define CLK_UART4 45
+#define CLK_UART5 46
+#define CLK_UART6 47
+#define CLK_DE1 48
+#define CLK_DE2 49
+#define CLK_I2SRX 50
+#define CLK_I2STX 51
+#define CLK_HDMI_AUDIO 52
+#define CLK_HDMI 53
+#define CLK_SPDIF 54
+#define CLK_NAND 55
+#define CLK_ECC 56
+#define CLK_RMII_REF 57
#define CLK_NR_CLKS (CLK_RMII_REF + 1)
--
2.27.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 3/6] clk: actions: Add APB, DMAC, GPIO clock support for Actions S500 SoC
2020-06-24 17:47 [PATCH v2 0/6] Add RMU and DMAC/GPIO clock support for Actions Semi S500 SoCs Cristian Ciocaltea
2020-06-24 17:47 ` [PATCH v2 1/6] clk: actions: Fix h_clk for Actions S500 SoC Cristian Ciocaltea
2020-06-24 17:47 ` [PATCH v2 2/6] dt-bindings: clock: Add APB, DMAC, GPIO bindings " Cristian Ciocaltea
@ 2020-06-24 17:47 ` Cristian Ciocaltea
2020-06-24 17:47 ` [PATCH v2 4/6] dt-bindings: reset: Add binding constants for Actions S500 RMU Cristian Ciocaltea
` (2 subsequent siblings)
5 siblings, 0 replies; 14+ messages in thread
From: Cristian Ciocaltea @ 2020-06-24 17:47 UTC (permalink / raw)
To: Stephen Boyd, Andreas Färber, Manivannan Sadhasivam,
Rob Herring, Michael Turquette, Philipp Zabel
Cc: linux-kernel, linux-clk, linux-arm-kernel, devicetree, linux-actions
Add support for the missing APB, DMAC and GPIO clocks in the Actions
Semi S500 SoC clock driver.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
---
drivers/clk/actions/owl-s500.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c
index 0eb83a0b70bc..025a8f6d6482 100644
--- a/drivers/clk/actions/owl-s500.c
+++ b/drivers/clk/actions/owl-s500.c
@@ -175,6 +175,8 @@ static OWL_MUX(dev_clk, "dev_clk", dev_clk_mux_p, CMU_DEVPLL, 12, 1, CLK_SET_RAT
static OWL_MUX(ahbprediv_clk, "ahbprediv_clk", ahbprediv_clk_mux_p, CMU_BUSCLK1, 8, 3, CLK_SET_RATE_PARENT);
/* gate clocks */
+static OWL_GATE(gpio_clk, "gpio_clk", "apb_clk", CMU_DEVCLKEN0, 18, 0, 0);
+static OWL_GATE(dmac_clk, "dmac_clk", "h_clk", CMU_DEVCLKEN0, 1, 0, 0);
static OWL_GATE(spi0_clk, "spi0_clk", "ahb_clk", CMU_DEVCLKEN1, 10, 0, CLK_IGNORE_UNUSED);
static OWL_GATE(spi1_clk, "spi1_clk", "ahb_clk", CMU_DEVCLKEN1, 11, 0, CLK_IGNORE_UNUSED);
static OWL_GATE(spi2_clk, "spi2_clk", "ahb_clk", CMU_DEVCLKEN1, 12, 0, CLK_IGNORE_UNUSED);
@@ -184,6 +186,7 @@ static OWL_GATE(hdmi_clk, "hdmi_clk", "hosc", CMU_DEVCLKEN1, 3, 0, 0);
/* divider clocks */
static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 12, 2, NULL, 0, 0);
+static OWL_DIVIDER(apb_clk, "apb_clk", "ahb_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0);
static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "ethernet_pll_clk", CMU_ETHERNETPLL, 1, 1, rmii_ref_div_table, 0, 0);
/* factor clocks */
@@ -428,6 +431,9 @@ static struct owl_clk_common *s500_clks[] = {
&spdif_clk.common,
&nand_clk.common,
&ecc_clk.common,
+ &apb_clk.common,
+ &dmac_clk.common,
+ &gpio_clk.common,
};
static struct clk_hw_onecell_data s500_hw_clks = {
@@ -484,6 +490,9 @@ static struct clk_hw_onecell_data s500_hw_clks = {
[CLK_SPDIF] = &spdif_clk.common.hw,
[CLK_NAND] = &nand_clk.common.hw,
[CLK_ECC] = &ecc_clk.common.hw,
+ [CLK_APB] = &apb_clk.common.hw,
+ [CLK_DMAC] = &dmac_clk.common.hw,
+ [CLK_GPIO] = &gpio_clk.common.hw,
},
.num = CLK_NR_CLKS,
};
--
2.27.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 4/6] dt-bindings: reset: Add binding constants for Actions S500 RMU
2020-06-24 17:47 [PATCH v2 0/6] Add RMU and DMAC/GPIO clock support for Actions Semi S500 SoCs Cristian Ciocaltea
` (2 preceding siblings ...)
2020-06-24 17:47 ` [PATCH v2 3/6] clk: actions: Add APB, DMAC, GPIO clock support " Cristian Ciocaltea
@ 2020-06-24 17:47 ` Cristian Ciocaltea
2020-06-26 12:14 ` Philipp Zabel
2020-06-24 17:47 ` [PATCH v2 5/6] clk: actions: Add Actions S500 SoC Reset Management Unit support Cristian Ciocaltea
2020-06-24 17:47 ` [PATCH v2 6/6] MAINTAINERS: Add reset binding entry for Actions Semi Owl SoCs Cristian Ciocaltea
5 siblings, 1 reply; 14+ messages in thread
From: Cristian Ciocaltea @ 2020-06-24 17:47 UTC (permalink / raw)
To: Stephen Boyd, Andreas Färber, Manivannan Sadhasivam,
Rob Herring, Michael Turquette, Philipp Zabel
Cc: linux-kernel, linux-clk, linux-arm-kernel, devicetree, linux-actions
Add device tree binding constants for Actions Semi S500 SoC Reset
Management Unit (RMU).
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
---
.../dt-bindings/reset/actions,s500-reset.h | 67 +++++++++++++++++++
1 file changed, 67 insertions(+)
create mode 100644 include/dt-bindings/reset/actions,s500-reset.h
diff --git a/include/dt-bindings/reset/actions,s500-reset.h b/include/dt-bindings/reset/actions,s500-reset.h
new file mode 100644
index 000000000000..f5d94176d10b
--- /dev/null
+++ b/include/dt-bindings/reset/actions,s500-reset.h
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Device Tree binding constants for Actions Semi S500 Reset Management Unit
+ *
+ * Copyright (c) 2014 Actions Semi Inc.
+ * Copyright (c) 2020 Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
+ */
+
+#ifndef __DT_BINDINGS_ACTIONS_S500_RESET_H
+#define __DT_BINDINGS_ACTIONS_S500_RESET_H
+
+#define RESET_DMAC 0
+#define RESET_NORIF 1
+#define RESET_DDR 2
+#define RESET_NANDC 3
+#define RESET_SD0 4
+#define RESET_SD1 5
+#define RESET_PCM1 6
+#define RESET_DE 7
+#define RESET_LCD 8
+#define RESET_SD2 9
+#define RESET_DSI 10
+#define RESET_CSI 11
+#define RESET_BISP 12
+#define RESET_KEY 13
+#define RESET_GPIO 14
+#define RESET_AUDIO 15
+#define RESET_PCM0 16
+#define RESET_VDE 17
+#define RESET_VCE 18
+#define RESET_GPU3D 19
+#define RESET_NIC301 20
+#define RESET_LENS 21
+#define RESET_PERIPHRESET 22
+#define RESET_USB2_0 23
+#define RESET_TVOUT 24
+#define RESET_HDMI 25
+#define RESET_HDCP2TX 26
+#define RESET_UART6 27
+#define RESET_UART0 28
+#define RESET_UART1 29
+#define RESET_UART2 30
+#define RESET_SPI0 31
+#define RESET_SPI1 32
+#define RESET_SPI2 33
+#define RESET_SPI3 34
+#define RESET_I2C0 35
+#define RESET_I2C1 36
+#define RESET_USB3 37
+#define RESET_UART3 38
+#define RESET_UART4 39
+#define RESET_UART5 40
+#define RESET_I2C2 41
+#define RESET_I2C3 42
+#define RESET_ETHERNET 43
+#define RESET_CHIPID 44
+#define RESET_USB2_1 45
+#define RESET_WD0RESET 46
+#define RESET_WD1RESET 47
+#define RESET_WD2RESET 48
+#define RESET_WD3RESET 49
+#define RESET_DBG0RESET 50
+#define RESET_DBG1RESET 51
+#define RESET_DBG2RESET 52
+#define RESET_DBG3RESET 53
+
+#endif /* __DT_BINDINGS_ACTIONS_S500_RESET_H */
--
2.27.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 5/6] clk: actions: Add Actions S500 SoC Reset Management Unit support
2020-06-24 17:47 [PATCH v2 0/6] Add RMU and DMAC/GPIO clock support for Actions Semi S500 SoCs Cristian Ciocaltea
` (3 preceding siblings ...)
2020-06-24 17:47 ` [PATCH v2 4/6] dt-bindings: reset: Add binding constants for Actions S500 RMU Cristian Ciocaltea
@ 2020-06-24 17:47 ` Cristian Ciocaltea
2020-06-26 13:52 ` Manivannan Sadhasivam
2020-06-24 17:47 ` [PATCH v2 6/6] MAINTAINERS: Add reset binding entry for Actions Semi Owl SoCs Cristian Ciocaltea
5 siblings, 1 reply; 14+ messages in thread
From: Cristian Ciocaltea @ 2020-06-24 17:47 UTC (permalink / raw)
To: Stephen Boyd, Andreas Färber, Manivannan Sadhasivam,
Rob Herring, Michael Turquette, Philipp Zabel
Cc: linux-kernel, linux-clk, linux-arm-kernel, devicetree, linux-actions
Add Reset Management Unit (RMU) support for Actions Semi S500 SoC.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
---
Changes in v2:
- Remove copyright as indicated by Stephen
drivers/clk/actions/owl-s500.c | 78 ++++++++++++++++++++++++++++++++++
1 file changed, 78 insertions(+)
diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c
index 025a8f6d6482..61bb224f6330 100644
--- a/drivers/clk/actions/owl-s500.c
+++ b/drivers/clk/actions/owl-s500.c
@@ -23,8 +23,10 @@
#include "owl-gate.h"
#include "owl-mux.h"
#include "owl-pll.h"
+#include "owl-reset.h"
#include <dt-bindings/clock/actions,s500-cmu.h>
+#include <dt-bindings/reset/actions,s500-reset.h>
#define CMU_COREPLL (0x0000)
#define CMU_DEVPLL (0x0004)
@@ -497,20 +499,96 @@ static struct clk_hw_onecell_data s500_hw_clks = {
.num = CLK_NR_CLKS,
};
+static const struct owl_reset_map s500_resets[] = {
+ [RESET_DMAC] = { CMU_DEVRST0, BIT(0) },
+ [RESET_NORIF] = { CMU_DEVRST0, BIT(1) },
+ [RESET_DDR] = { CMU_DEVRST0, BIT(2) },
+ [RESET_NANDC] = { CMU_DEVRST0, BIT(3) },
+ [RESET_SD0] = { CMU_DEVRST0, BIT(4) },
+ [RESET_SD1] = { CMU_DEVRST0, BIT(5) },
+ [RESET_PCM1] = { CMU_DEVRST0, BIT(6) },
+ [RESET_DE] = { CMU_DEVRST0, BIT(7) },
+ [RESET_LCD] = { CMU_DEVRST0, BIT(8) },
+ [RESET_SD2] = { CMU_DEVRST0, BIT(9) },
+ [RESET_DSI] = { CMU_DEVRST0, BIT(10) },
+ [RESET_CSI] = { CMU_DEVRST0, BIT(11) },
+ [RESET_BISP] = { CMU_DEVRST0, BIT(12) },
+ [RESET_KEY] = { CMU_DEVRST0, BIT(14) },
+ [RESET_GPIO] = { CMU_DEVRST0, BIT(15) },
+ [RESET_AUDIO] = { CMU_DEVRST0, BIT(17) },
+ [RESET_PCM0] = { CMU_DEVRST0, BIT(18) },
+ [RESET_VDE] = { CMU_DEVRST0, BIT(19) },
+ [RESET_VCE] = { CMU_DEVRST0, BIT(20) },
+ [RESET_GPU3D] = { CMU_DEVRST0, BIT(22) },
+ [RESET_NIC301] = { CMU_DEVRST0, BIT(23) },
+ [RESET_LENS] = { CMU_DEVRST0, BIT(26) },
+ [RESET_PERIPHRESET] = { CMU_DEVRST0, BIT(27) },
+ [RESET_USB2_0] = { CMU_DEVRST1, BIT(0) },
+ [RESET_TVOUT] = { CMU_DEVRST1, BIT(1) },
+ [RESET_HDMI] = { CMU_DEVRST1, BIT(2) },
+ [RESET_HDCP2TX] = { CMU_DEVRST1, BIT(3) },
+ [RESET_UART6] = { CMU_DEVRST1, BIT(4) },
+ [RESET_UART0] = { CMU_DEVRST1, BIT(5) },
+ [RESET_UART1] = { CMU_DEVRST1, BIT(6) },
+ [RESET_UART2] = { CMU_DEVRST1, BIT(7) },
+ [RESET_SPI0] = { CMU_DEVRST1, BIT(8) },
+ [RESET_SPI1] = { CMU_DEVRST1, BIT(9) },
+ [RESET_SPI2] = { CMU_DEVRST1, BIT(10) },
+ [RESET_SPI3] = { CMU_DEVRST1, BIT(11) },
+ [RESET_I2C0] = { CMU_DEVRST1, BIT(12) },
+ [RESET_I2C1] = { CMU_DEVRST1, BIT(13) },
+ [RESET_USB3] = { CMU_DEVRST1, BIT(14) },
+ [RESET_UART3] = { CMU_DEVRST1, BIT(15) },
+ [RESET_UART4] = { CMU_DEVRST1, BIT(16) },
+ [RESET_UART5] = { CMU_DEVRST1, BIT(17) },
+ [RESET_I2C2] = { CMU_DEVRST1, BIT(18) },
+ [RESET_I2C3] = { CMU_DEVRST1, BIT(19) },
+ [RESET_ETHERNET] = { CMU_DEVRST1, BIT(20) },
+ [RESET_CHIPID] = { CMU_DEVRST1, BIT(21) },
+ [RESET_USB2_1] = { CMU_DEVRST1, BIT(22) },
+ [RESET_WD0RESET] = { CMU_DEVRST1, BIT(24) },
+ [RESET_WD1RESET] = { CMU_DEVRST1, BIT(25) },
+ [RESET_WD2RESET] = { CMU_DEVRST1, BIT(26) },
+ [RESET_WD3RESET] = { CMU_DEVRST1, BIT(27) },
+ [RESET_DBG0RESET] = { CMU_DEVRST1, BIT(28) },
+ [RESET_DBG1RESET] = { CMU_DEVRST1, BIT(29) },
+ [RESET_DBG2RESET] = { CMU_DEVRST1, BIT(30) },
+ [RESET_DBG3RESET] = { CMU_DEVRST1, BIT(31) },
+};
+
static struct owl_clk_desc s500_clk_desc = {
.clks = s500_clks,
.num_clks = ARRAY_SIZE(s500_clks),
.hw_clks = &s500_hw_clks,
+
+ .resets = s500_resets,
+ .num_resets = ARRAY_SIZE(s500_resets),
};
static int s500_clk_probe(struct platform_device *pdev)
{
struct owl_clk_desc *desc;
+ struct owl_reset *reset;
+ int ret;
desc = &s500_clk_desc;
owl_clk_regmap_init(pdev, desc);
+ reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL);
+ if (!reset)
+ return -ENOMEM;
+
+ reset->rcdev.of_node = pdev->dev.of_node;
+ reset->rcdev.ops = &owl_reset_ops;
+ reset->rcdev.nr_resets = desc->num_resets;
+ reset->reset_map = desc->resets;
+ reset->regmap = desc->regmap;
+
+ ret = devm_reset_controller_register(&pdev->dev, &reset->rcdev);
+ if (ret)
+ dev_err(&pdev->dev, "Failed to register reset controller\n");
+
return owl_clk_probe(&pdev->dev, desc->hw_clks);
}
--
2.27.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 6/6] MAINTAINERS: Add reset binding entry for Actions Semi Owl SoCs
2020-06-24 17:47 [PATCH v2 0/6] Add RMU and DMAC/GPIO clock support for Actions Semi S500 SoCs Cristian Ciocaltea
` (4 preceding siblings ...)
2020-06-24 17:47 ` [PATCH v2 5/6] clk: actions: Add Actions S500 SoC Reset Management Unit support Cristian Ciocaltea
@ 2020-06-24 17:47 ` Cristian Ciocaltea
2020-06-26 13:54 ` Manivannan Sadhasivam
5 siblings, 1 reply; 14+ messages in thread
From: Cristian Ciocaltea @ 2020-06-24 17:47 UTC (permalink / raw)
To: Stephen Boyd, Andreas Färber, Manivannan Sadhasivam,
Rob Herring, Michael Turquette, Philipp Zabel
Cc: linux-kernel, linux-clk, linux-arm-kernel, devicetree, linux-actions
Add a reset binding entry to match all members of Actions Semi Owl SoCs.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7b5ffd646c6b..e6285c13bab0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1533,6 +1533,7 @@ F: drivers/mmc/host/owl-mmc.c
F: drivers/pinctrl/actions/*
F: drivers/soc/actions/
F: include/dt-bindings/power/owl-*
+F: include/dt-bindings/reset/actions,*-reset.h
F: include/linux/soc/actions/
N: owl
--
2.27.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v2 2/6] dt-bindings: clock: Add APB, DMAC, GPIO bindings for Actions S500 SoC
[not found] ` <159303816030.62212.1603754983340876289@swboyd.mtv.corp.google.com>
@ 2020-06-25 12:50 ` Cristian Ciocaltea
0 siblings, 0 replies; 14+ messages in thread
From: Cristian Ciocaltea @ 2020-06-25 12:50 UTC (permalink / raw)
To: Stephen Boyd
Cc: Andreas Färber, Manivannan Sadhasivam, Michael Turquette,
Philipp Zabel, Rob Herring, linux-kernel, linux-clk,
linux-arm-kernel, devicetree, linux-actions
On Wed, Jun 24, 2020 at 03:36:00PM -0700, Stephen Boyd wrote:
> Quoting Cristian Ciocaltea (2020-06-24 10:47:53)
> > diff --git a/include/dt-bindings/clock/actions,s500-cmu.h b/include/dt-bindings/clock/actions,s500-cmu.h
> > index 030981cd2d56..a391d1651257 100644
> > --- a/include/dt-bindings/clock/actions,s500-cmu.h
> > +++ b/include/dt-bindings/clock/actions,s500-cmu.h
> > @@ -33,45 +33,48 @@
> > #define CLK_BISP 15
> > #define CLK_VCE 16
> > #define CLK_VDE 17
> > +#define CLK_APB 18
> > +#define CLK_DMAC 19
> >
> > /* peripheral device clock */
> > -#define CLK_TIMER 18
> > -#define CLK_I2C0 19
> > -#define CLK_I2C1 20
> > -#define CLK_I2C2 21
> > -#define CLK_I2C3 22
> > -#define CLK_PWM0 23
> > -#define CLK_PWM1 24
> > -#define CLK_PWM2 25
> > -#define CLK_PWM3 26
> > -#define CLK_PWM4 27
> > -#define CLK_PWM5 28
> > -#define CLK_SD0 29
> > -#define CLK_SD1 30
> > -#define CLK_SD2 31
> > -#define CLK_SENSOR0 32
> > -#define CLK_SENSOR1 33
> > -#define CLK_SPI0 34
> > -#define CLK_SPI1 35
> > -#define CLK_SPI2 36
> > -#define CLK_SPI3 37
> > -#define CLK_UART0 38
> > -#define CLK_UART1 39
> > -#define CLK_UART2 40
> > -#define CLK_UART3 41
> > -#define CLK_UART4 42
> > -#define CLK_UART5 43
> > -#define CLK_UART6 44
> > -#define CLK_DE1 45
> > -#define CLK_DE2 46
> > -#define CLK_I2SRX 47
> > -#define CLK_I2STX 48
> > -#define CLK_HDMI_AUDIO 49
> > -#define CLK_HDMI 50
> > -#define CLK_SPDIF 51
> > -#define CLK_NAND 52
> > -#define CLK_ECC 53
> > -#define CLK_RMII_REF 54
>
> This number can't change. Just add new defines after and update the
> CLK_NR_CLKS define.
Thanks for pointing this out, I wasn't aware of this restriction.
I will add CLK_GPIO immediately after CLK_RMII_REF, since it is part
of the same peripheral device clock group, then I continue with CLK_APB
and CLK_DMAC, documenting that they belong to the system clock group
above.
>
> > +#define CLK_GPIO 20
> > +#define CLK_TIMER 21
> > +#define CLK_I2C0 22
> > +#define CLK_I2C1 23
> > +#define CLK_I2C2 24
> > +#define CLK_I2C3 25
> > +#define CLK_PWM0 26
> > +#define CLK_PWM1 27
> > +#define CLK_PWM2 28
> > +#define CLK_PWM3 29
> > +#define CLK_PWM4 30
> > +#define CLK_PWM5 31
> > +#define CLK_SD0 32
> > +#define CLK_SD1 33
> > +#define CLK_SD2 34
> > +#define CLK_SENSOR0 35
> > +#define CLK_SENSOR1 36
> > +#define CLK_SPI0 37
> > +#define CLK_SPI1 38
> > +#define CLK_SPI2 39
> > +#define CLK_SPI3 40
> > +#define CLK_UART0 41
> > +#define CLK_UART1 42
> > +#define CLK_UART2 43
> > +#define CLK_UART3 44
> > +#define CLK_UART4 45
> > +#define CLK_UART5 46
> > +#define CLK_UART6 47
> > +#define CLK_DE1 48
> > +#define CLK_DE2 49
> > +#define CLK_I2SRX 50
> > +#define CLK_I2STX 51
> > +#define CLK_HDMI_AUDIO 52
> > +#define CLK_HDMI 53
> > +#define CLK_SPDIF 54
> > +#define CLK_NAND 55
> > +#define CLK_ECC 56
> > +#define CLK_RMII_REF 57
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 4/6] dt-bindings: reset: Add binding constants for Actions S500 RMU
2020-06-24 17:47 ` [PATCH v2 4/6] dt-bindings: reset: Add binding constants for Actions S500 RMU Cristian Ciocaltea
@ 2020-06-26 12:14 ` Philipp Zabel
0 siblings, 0 replies; 14+ messages in thread
From: Philipp Zabel @ 2020-06-26 12:14 UTC (permalink / raw)
To: Cristian Ciocaltea, Stephen Boyd, Andreas Färber,
Manivannan Sadhasivam, Rob Herring, Michael Turquette
Cc: linux-kernel, linux-clk, linux-arm-kernel, devicetree, linux-actions
On Wed, 2020-06-24 at 20:47 +0300, Cristian Ciocaltea wrote:
> Add device tree binding constants for Actions Semi S500 SoC Reset
> Management Unit (RMU).
>
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
to be merged through the clock tree, required by the following patch:
"clk: actions: Add Actions S500 SoC Reset Management Unit support".
regards
Philipp
> ---
> .../dt-bindings/reset/actions,s500-reset.h | 67 +++++++++++++++++++
> 1 file changed, 67 insertions(+)
> create mode 100644 include/dt-bindings/reset/actions,s500-reset.h
>
> diff --git a/include/dt-bindings/reset/actions,s500-reset.h b/include/dt-bindings/reset/actions,s500-reset.h
> new file mode 100644
> index 000000000000..f5d94176d10b
> --- /dev/null
> +++ b/include/dt-bindings/reset/actions,s500-reset.h
> @@ -0,0 +1,67 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Device Tree binding constants for Actions Semi S500 Reset Management Unit
> + *
> + * Copyright (c) 2014 Actions Semi Inc.
> + * Copyright (c) 2020 Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> + */
> +
> +#ifndef __DT_BINDINGS_ACTIONS_S500_RESET_H
> +#define __DT_BINDINGS_ACTIONS_S500_RESET_H
> +
> +#define RESET_DMAC 0
> +#define RESET_NORIF 1
> +#define RESET_DDR 2
> +#define RESET_NANDC 3
> +#define RESET_SD0 4
> +#define RESET_SD1 5
> +#define RESET_PCM1 6
> +#define RESET_DE 7
> +#define RESET_LCD 8
> +#define RESET_SD2 9
> +#define RESET_DSI 10
> +#define RESET_CSI 11
> +#define RESET_BISP 12
> +#define RESET_KEY 13
> +#define RESET_GPIO 14
> +#define RESET_AUDIO 15
> +#define RESET_PCM0 16
> +#define RESET_VDE 17
> +#define RESET_VCE 18
> +#define RESET_GPU3D 19
> +#define RESET_NIC301 20
> +#define RESET_LENS 21
> +#define RESET_PERIPHRESET 22
> +#define RESET_USB2_0 23
> +#define RESET_TVOUT 24
> +#define RESET_HDMI 25
> +#define RESET_HDCP2TX 26
> +#define RESET_UART6 27
> +#define RESET_UART0 28
> +#define RESET_UART1 29
> +#define RESET_UART2 30
> +#define RESET_SPI0 31
> +#define RESET_SPI1 32
> +#define RESET_SPI2 33
> +#define RESET_SPI3 34
> +#define RESET_I2C0 35
> +#define RESET_I2C1 36
> +#define RESET_USB3 37
> +#define RESET_UART3 38
> +#define RESET_UART4 39
> +#define RESET_UART5 40
> +#define RESET_I2C2 41
> +#define RESET_I2C3 42
> +#define RESET_ETHERNET 43
> +#define RESET_CHIPID 44
> +#define RESET_USB2_1 45
> +#define RESET_WD0RESET 46
> +#define RESET_WD1RESET 47
> +#define RESET_WD2RESET 48
> +#define RESET_WD3RESET 49
> +#define RESET_DBG0RESET 50
> +#define RESET_DBG1RESET 51
> +#define RESET_DBG2RESET 52
> +#define RESET_DBG3RESET 53
> +
> +#endif /* __DT_BINDINGS_ACTIONS_S500_RESET_H */
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 1/6] clk: actions: Fix h_clk for Actions S500 SoC
2020-06-24 17:47 ` [PATCH v2 1/6] clk: actions: Fix h_clk for Actions S500 SoC Cristian Ciocaltea
@ 2020-06-26 13:45 ` Manivannan Sadhasivam
2020-06-26 15:49 ` Cristian Ciocaltea
0 siblings, 1 reply; 14+ messages in thread
From: Manivannan Sadhasivam @ 2020-06-26 13:45 UTC (permalink / raw)
To: Cristian Ciocaltea
Cc: Stephen Boyd, Andreas Färber, Rob Herring,
Michael Turquette, Philipp Zabel, linux-kernel, linux-clk,
linux-arm-kernel, devicetree, linux-actions
On Wed, Jun 24, 2020 at 08:47:52PM +0300, Cristian Ciocaltea wrote:
> The h_clk clock in the Actions Semi S500 SoC clock driver has an
> invalid parent. Replace with the correct one.
>
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
You should add fixes tag for this patch and it needs to be backported as well.
Thanks,
Mani
> ---
> drivers/clk/actions/owl-s500.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c
> index e2007ac4d235..0eb83a0b70bc 100644
> --- a/drivers/clk/actions/owl-s500.c
> +++ b/drivers/clk/actions/owl-s500.c
> @@ -183,7 +183,7 @@ static OWL_GATE(timer_clk, "timer_clk", "hosc", CMU_DEVCLKEN1, 27, 0, 0);
> static OWL_GATE(hdmi_clk, "hdmi_clk", "hosc", CMU_DEVCLKEN1, 3, 0, 0);
>
> /* divider clocks */
> -static OWL_DIVIDER(h_clk, "h_clk", "ahbprevdiv_clk", CMU_BUSCLK1, 12, 2, NULL, 0, 0);
> +static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 12, 2, NULL, 0, 0);
> static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "ethernet_pll_clk", CMU_ETHERNETPLL, 1, 1, rmii_ref_div_table, 0, 0);
>
> /* factor clocks */
> --
> 2.27.0
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 5/6] clk: actions: Add Actions S500 SoC Reset Management Unit support
2020-06-24 17:47 ` [PATCH v2 5/6] clk: actions: Add Actions S500 SoC Reset Management Unit support Cristian Ciocaltea
@ 2020-06-26 13:52 ` Manivannan Sadhasivam
0 siblings, 0 replies; 14+ messages in thread
From: Manivannan Sadhasivam @ 2020-06-26 13:52 UTC (permalink / raw)
To: Cristian Ciocaltea
Cc: Stephen Boyd, Andreas Färber, Rob Herring,
Michael Turquette, Philipp Zabel, linux-kernel, linux-clk,
linux-arm-kernel, devicetree, linux-actions
On Wed, Jun 24, 2020 at 08:47:56PM +0300, Cristian Ciocaltea wrote:
> Add Reset Management Unit (RMU) support for Actions Semi S500 SoC.
>
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Thanks,
Mani
> ---
> Changes in v2:
> - Remove copyright as indicated by Stephen
>
> drivers/clk/actions/owl-s500.c | 78 ++++++++++++++++++++++++++++++++++
> 1 file changed, 78 insertions(+)
>
> diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c
> index 025a8f6d6482..61bb224f6330 100644
> --- a/drivers/clk/actions/owl-s500.c
> +++ b/drivers/clk/actions/owl-s500.c
> @@ -23,8 +23,10 @@
> #include "owl-gate.h"
> #include "owl-mux.h"
> #include "owl-pll.h"
> +#include "owl-reset.h"
>
> #include <dt-bindings/clock/actions,s500-cmu.h>
> +#include <dt-bindings/reset/actions,s500-reset.h>
>
> #define CMU_COREPLL (0x0000)
> #define CMU_DEVPLL (0x0004)
> @@ -497,20 +499,96 @@ static struct clk_hw_onecell_data s500_hw_clks = {
> .num = CLK_NR_CLKS,
> };
>
> +static const struct owl_reset_map s500_resets[] = {
> + [RESET_DMAC] = { CMU_DEVRST0, BIT(0) },
> + [RESET_NORIF] = { CMU_DEVRST0, BIT(1) },
> + [RESET_DDR] = { CMU_DEVRST0, BIT(2) },
> + [RESET_NANDC] = { CMU_DEVRST0, BIT(3) },
> + [RESET_SD0] = { CMU_DEVRST0, BIT(4) },
> + [RESET_SD1] = { CMU_DEVRST0, BIT(5) },
> + [RESET_PCM1] = { CMU_DEVRST0, BIT(6) },
> + [RESET_DE] = { CMU_DEVRST0, BIT(7) },
> + [RESET_LCD] = { CMU_DEVRST0, BIT(8) },
> + [RESET_SD2] = { CMU_DEVRST0, BIT(9) },
> + [RESET_DSI] = { CMU_DEVRST0, BIT(10) },
> + [RESET_CSI] = { CMU_DEVRST0, BIT(11) },
> + [RESET_BISP] = { CMU_DEVRST0, BIT(12) },
> + [RESET_KEY] = { CMU_DEVRST0, BIT(14) },
> + [RESET_GPIO] = { CMU_DEVRST0, BIT(15) },
> + [RESET_AUDIO] = { CMU_DEVRST0, BIT(17) },
> + [RESET_PCM0] = { CMU_DEVRST0, BIT(18) },
> + [RESET_VDE] = { CMU_DEVRST0, BIT(19) },
> + [RESET_VCE] = { CMU_DEVRST0, BIT(20) },
> + [RESET_GPU3D] = { CMU_DEVRST0, BIT(22) },
> + [RESET_NIC301] = { CMU_DEVRST0, BIT(23) },
> + [RESET_LENS] = { CMU_DEVRST0, BIT(26) },
> + [RESET_PERIPHRESET] = { CMU_DEVRST0, BIT(27) },
> + [RESET_USB2_0] = { CMU_DEVRST1, BIT(0) },
> + [RESET_TVOUT] = { CMU_DEVRST1, BIT(1) },
> + [RESET_HDMI] = { CMU_DEVRST1, BIT(2) },
> + [RESET_HDCP2TX] = { CMU_DEVRST1, BIT(3) },
> + [RESET_UART6] = { CMU_DEVRST1, BIT(4) },
> + [RESET_UART0] = { CMU_DEVRST1, BIT(5) },
> + [RESET_UART1] = { CMU_DEVRST1, BIT(6) },
> + [RESET_UART2] = { CMU_DEVRST1, BIT(7) },
> + [RESET_SPI0] = { CMU_DEVRST1, BIT(8) },
> + [RESET_SPI1] = { CMU_DEVRST1, BIT(9) },
> + [RESET_SPI2] = { CMU_DEVRST1, BIT(10) },
> + [RESET_SPI3] = { CMU_DEVRST1, BIT(11) },
> + [RESET_I2C0] = { CMU_DEVRST1, BIT(12) },
> + [RESET_I2C1] = { CMU_DEVRST1, BIT(13) },
> + [RESET_USB3] = { CMU_DEVRST1, BIT(14) },
> + [RESET_UART3] = { CMU_DEVRST1, BIT(15) },
> + [RESET_UART4] = { CMU_DEVRST1, BIT(16) },
> + [RESET_UART5] = { CMU_DEVRST1, BIT(17) },
> + [RESET_I2C2] = { CMU_DEVRST1, BIT(18) },
> + [RESET_I2C3] = { CMU_DEVRST1, BIT(19) },
> + [RESET_ETHERNET] = { CMU_DEVRST1, BIT(20) },
> + [RESET_CHIPID] = { CMU_DEVRST1, BIT(21) },
> + [RESET_USB2_1] = { CMU_DEVRST1, BIT(22) },
> + [RESET_WD0RESET] = { CMU_DEVRST1, BIT(24) },
> + [RESET_WD1RESET] = { CMU_DEVRST1, BIT(25) },
> + [RESET_WD2RESET] = { CMU_DEVRST1, BIT(26) },
> + [RESET_WD3RESET] = { CMU_DEVRST1, BIT(27) },
> + [RESET_DBG0RESET] = { CMU_DEVRST1, BIT(28) },
> + [RESET_DBG1RESET] = { CMU_DEVRST1, BIT(29) },
> + [RESET_DBG2RESET] = { CMU_DEVRST1, BIT(30) },
> + [RESET_DBG3RESET] = { CMU_DEVRST1, BIT(31) },
> +};
> +
> static struct owl_clk_desc s500_clk_desc = {
> .clks = s500_clks,
> .num_clks = ARRAY_SIZE(s500_clks),
>
> .hw_clks = &s500_hw_clks,
> +
> + .resets = s500_resets,
> + .num_resets = ARRAY_SIZE(s500_resets),
> };
>
> static int s500_clk_probe(struct platform_device *pdev)
> {
> struct owl_clk_desc *desc;
> + struct owl_reset *reset;
> + int ret;
>
> desc = &s500_clk_desc;
> owl_clk_regmap_init(pdev, desc);
>
> + reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL);
> + if (!reset)
> + return -ENOMEM;
> +
> + reset->rcdev.of_node = pdev->dev.of_node;
> + reset->rcdev.ops = &owl_reset_ops;
> + reset->rcdev.nr_resets = desc->num_resets;
> + reset->reset_map = desc->resets;
> + reset->regmap = desc->regmap;
> +
> + ret = devm_reset_controller_register(&pdev->dev, &reset->rcdev);
> + if (ret)
> + dev_err(&pdev->dev, "Failed to register reset controller\n");
> +
> return owl_clk_probe(&pdev->dev, desc->hw_clks);
> }
>
> --
> 2.27.0
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 6/6] MAINTAINERS: Add reset binding entry for Actions Semi Owl SoCs
2020-06-24 17:47 ` [PATCH v2 6/6] MAINTAINERS: Add reset binding entry for Actions Semi Owl SoCs Cristian Ciocaltea
@ 2020-06-26 13:54 ` Manivannan Sadhasivam
2020-06-26 15:58 ` Cristian Ciocaltea
0 siblings, 1 reply; 14+ messages in thread
From: Manivannan Sadhasivam @ 2020-06-26 13:54 UTC (permalink / raw)
To: Cristian Ciocaltea
Cc: Stephen Boyd, Andreas Färber, Rob Herring,
Michael Turquette, Philipp Zabel, linux-kernel, linux-clk,
linux-arm-kernel, devicetree, linux-actions
On Wed, Jun 24, 2020 at 08:47:57PM +0300, Cristian Ciocaltea wrote:
> Add a reset binding entry to match all members of Actions Semi Owl SoCs.
>
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> ---
> MAINTAINERS | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 7b5ffd646c6b..e6285c13bab0 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1533,6 +1533,7 @@ F: drivers/mmc/host/owl-mmc.c
> F: drivers/pinctrl/actions/*
> F: drivers/soc/actions/
> F: include/dt-bindings/power/owl-*
> +F: include/dt-bindings/reset/actions,*-reset.h
You can just use, reset/actions,*
Thanks,
Mani
> F: include/linux/soc/actions/
> N: owl
>
> --
> 2.27.0
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 1/6] clk: actions: Fix h_clk for Actions S500 SoC
2020-06-26 13:45 ` Manivannan Sadhasivam
@ 2020-06-26 15:49 ` Cristian Ciocaltea
0 siblings, 0 replies; 14+ messages in thread
From: Cristian Ciocaltea @ 2020-06-26 15:49 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: Stephen Boyd, Andreas Färber, Rob Herring,
Michael Turquette, Philipp Zabel, linux-kernel, linux-clk,
linux-arm-kernel, devicetree, linux-actions
On Fri, Jun 26, 2020 at 07:15:41PM +0530, Manivannan Sadhasivam wrote:
> On Wed, Jun 24, 2020 at 08:47:52PM +0300, Cristian Ciocaltea wrote:
> > The h_clk clock in the Actions Semi S500 SoC clock driver has an
> > invalid parent. Replace with the correct one.
> >
> > Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
>
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
>
> You should add fixes tag for this patch and it needs to be backported as well.
>
> Thanks,
> Mani
Right, I added the tag:
Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC")
Thanks,
Cristi
>
> > ---
> > drivers/clk/actions/owl-s500.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c
> > index e2007ac4d235..0eb83a0b70bc 100644
> > --- a/drivers/clk/actions/owl-s500.c
> > +++ b/drivers/clk/actions/owl-s500.c
> > @@ -183,7 +183,7 @@ static OWL_GATE(timer_clk, "timer_clk", "hosc", CMU_DEVCLKEN1, 27, 0, 0);
> > static OWL_GATE(hdmi_clk, "hdmi_clk", "hosc", CMU_DEVCLKEN1, 3, 0, 0);
> >
> > /* divider clocks */
> > -static OWL_DIVIDER(h_clk, "h_clk", "ahbprevdiv_clk", CMU_BUSCLK1, 12, 2, NULL, 0, 0);
> > +static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 12, 2, NULL, 0, 0);
> > static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "ethernet_pll_clk", CMU_ETHERNETPLL, 1, 1, rmii_ref_div_table, 0, 0);
> >
> > /* factor clocks */
> > --
> > 2.27.0
> >
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 6/6] MAINTAINERS: Add reset binding entry for Actions Semi Owl SoCs
2020-06-26 13:54 ` Manivannan Sadhasivam
@ 2020-06-26 15:58 ` Cristian Ciocaltea
0 siblings, 0 replies; 14+ messages in thread
From: Cristian Ciocaltea @ 2020-06-26 15:58 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: Stephen Boyd, Andreas Färber, Rob Herring,
Michael Turquette, Philipp Zabel, linux-kernel, linux-clk,
linux-arm-kernel, devicetree, linux-actions
On Fri, Jun 26, 2020 at 07:24:16PM +0530, Manivannan Sadhasivam wrote:
> On Wed, Jun 24, 2020 at 08:47:57PM +0300, Cristian Ciocaltea wrote:
> > Add a reset binding entry to match all members of Actions Semi Owl SoCs.
> >
> > Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> > ---
> > MAINTAINERS | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 7b5ffd646c6b..e6285c13bab0 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -1533,6 +1533,7 @@ F: drivers/mmc/host/owl-mmc.c
> > F: drivers/pinctrl/actions/*
> > F: drivers/soc/actions/
> > F: include/dt-bindings/power/owl-*
> > +F: include/dt-bindings/reset/actions,*-reset.h
>
> You can just use, reset/actions,*
>
> Thanks,
> Mani
Done, thanks!
>
> > F: include/linux/soc/actions/
> > N: owl
> >
> > --
> > 2.27.0
> >
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2020-06-26 15:59 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-06-24 17:47 [PATCH v2 0/6] Add RMU and DMAC/GPIO clock support for Actions Semi S500 SoCs Cristian Ciocaltea
2020-06-24 17:47 ` [PATCH v2 1/6] clk: actions: Fix h_clk for Actions S500 SoC Cristian Ciocaltea
2020-06-26 13:45 ` Manivannan Sadhasivam
2020-06-26 15:49 ` Cristian Ciocaltea
2020-06-24 17:47 ` [PATCH v2 2/6] dt-bindings: clock: Add APB, DMAC, GPIO bindings " Cristian Ciocaltea
[not found] ` <159303816030.62212.1603754983340876289@swboyd.mtv.corp.google.com>
2020-06-25 12:50 ` Cristian Ciocaltea
2020-06-24 17:47 ` [PATCH v2 3/6] clk: actions: Add APB, DMAC, GPIO clock support " Cristian Ciocaltea
2020-06-24 17:47 ` [PATCH v2 4/6] dt-bindings: reset: Add binding constants for Actions S500 RMU Cristian Ciocaltea
2020-06-26 12:14 ` Philipp Zabel
2020-06-24 17:47 ` [PATCH v2 5/6] clk: actions: Add Actions S500 SoC Reset Management Unit support Cristian Ciocaltea
2020-06-26 13:52 ` Manivannan Sadhasivam
2020-06-24 17:47 ` [PATCH v2 6/6] MAINTAINERS: Add reset binding entry for Actions Semi Owl SoCs Cristian Ciocaltea
2020-06-26 13:54 ` Manivannan Sadhasivam
2020-06-26 15:58 ` Cristian Ciocaltea
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